Datasheet LTC3873-5 (Analog Devices) - 10

LTC3873-5
APPLICATIONS INFORMATION Turns Ratios
and gate-to-drain charges (QGS and QGD, respectively), the maximum drain current (I Due to the use of the external feedback resistor divider D(MAX)) and the MOSFET’s thermal resistances (R ratio to set output voltage, the user has relative freedom TH(JC) and RTH(JA)). in selecting a transformer turns ratio to suit a given ap-
Current Limit Programming
plication. Simple ratios of small integers, e.g., 1:1, 2:1, 3:2, etc. can be employed which yield more freedom in setting During the switch on-time, the control circuit limits the total turns and mutual inductance. Simple integer turns maximum voltage drop across the current sense com- ratios also facilitate the use of “off-the-shelf” confi gurable ponent to about 270mV, 100mV and 170mV at low duty transformers such as the Coiltronics VERSA-PAC series cycle with IPRG tied to VIN, GND or left fl oating respec- in applications with high input to output voltage ratios. tively. For boost applications with RDS(ON) sensing, refer For example, if a 6-winding VERSA-PAC is used with three to the LTC3872 data sheet for the selection of MOSFET windings in series on the primary and three windings in RDS(ON). parallel on the secondary, a 3:1 turns ratio will be achieved. MOSFETs have conduction losses (I2R) and switching Turns ratio can be chosen on the basis of desired duty losses. For VDS < 20V, high current effi ciency generally cycle. However, remember that the input supply voltage improves with large MOSFETs with low RDS(ON), while plus the secondary-to-primary referred version of the for VDS > 20V the transition losses rapidly increase to the fl yback pulse (including leakage spike) must not exceed point that the use of a higher RDS(ON) device with lower the allowed external MOSFET breakdown rating. reverse transfer capacitance, CRSS, actually provides higher effi ciency.
Leakage Inductance
Transformer leakage inductance (on either the primary
Output Capacitors
or secondary) causes a voltage spike to occur after the The output capacitor is normally chosen by its effective output switch (Q1) turn-off. This is increasingly prominent series resistance (ESR), which determines output ripple at higher load currents where more stored energy must voltage and affects effi ciency. Low ESR ceramic capaci- be dissipated. In some cases a “snubber” circuit will be tors are often used to minimize the output ripple. Boost required to avoid overvoltage breakdown at the MOSFET’s regulators have large RMS ripple current in the output drain node. Application Note 19 is a good reference on capacitor that must be rated to handle the current. The snubber design. A bifi lar or similar winding technique is a output ripple current (RMS) is: good way to minimize troublesome leakage inductances. However, remember that this will limit the primary-to- V – V OUT IN MIN ( ) I ≈ I • secondary breakdown voltage, so bifi lar winding is not RMS C ( OUT) OUT MA ( X) VIN MIN ( ) always practical. Output ripple is then simply:
Power MOSFET Selection
VOUT = RESR(ΔIL(RMS)) The power MOSFET serves two purposes in the LTC3873-5: The output capacitor for fl yback converter should have a it represents the main switching element in the power path ripple current rating greater than: and its RDS(ON) represents the current sensing element for the control loop. Important parameters for the power DMAX MOSFET include the drain-to-source breakdown voltage I = I RMS OUT • 1– D (BV MAX DSS), the threshold voltage (VGS(TH)), the on-resistance (RDS(ON)) versus gate-to-source voltage, the gate-to-source 38735fb 10