Datasheet LTC3873 (Analog Devices) - 8
| 制造商 | Analog Devices |
| 描述 | No RSENSE Constant Frequency Current Mode Boost/Flyback/SEPIC DC/DC Controller |
| 页数 / 页 | 18 / 8 — OPERATION. Light Load Operation. Soft-Start. Current Sense. Figure 4. … |
| 文件格式/大小 | PDF / 267 Kb |
| 文件语言 | 英语 |
OPERATION. Light Load Operation. Soft-Start. Current Sense. Figure 4. Maximum SENSE Threshold Voltage vs Duty Cycle
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LTC3873
OPERATION
(nominally 8.4V) at least momentarily to enable LTC3873
Light Load Operation
operation. The VCC voltage is then allowed to fall to VTURNOFF Under very light load current conditions, the I (nominally 4V) before undervoltage lockout disables the TH pin volt- age will be very close to the zero current level of 0.85V. LTC3873. This wide UVLO hysteresis range supports the As the load current decreases further, an internal offset at use of trickle charger on the flyback transformer to power the current comparator input will assure that the current the LTC3873—see the section, VCC Bias Power. The RUN/SS comparator remains tripped (even at zero load current) and pin can be driven below VSHDN (nominally 0.7V) to force the regulator will start to skip cycles in order to maintain the LTC3873 into shutdwn. When the chip is off, the input regulation. This behavior allows the regulator to maintain supply current is typically only 55μA. constant frequency down to very light loads, resulting in low
Soft-Start
output ripple as well as low audible noise and reduced RF Leave the RUN/SS pin open to use the internal 3.3ms interference while providing high light load efficiency. soft-start. During the internal soft-start, a voltage ramp
Current Sense
limits the VITH. 3.3ms is required for ITH to ramp from zero current level to full current level. The soft-start can During the switch on-time, the control circuit limits the be lengthened by placing an external capacitor from the maximum voltage drop across the current sense com- RUN/SS pin to the GND. A 3μA current will charge the ponent to about 295mV, 110mV and 185mV at low duty capacitor, pulling the RUN/SS pin above the shutdown cycle with IPRG tied to VIN, GND or left floating respec- threshold and a 15µA pull-up current will continue to ramp tively. It is reduced with increasing duty cycle as shown RUN/SS to limit VITH during the start-up. When RUN/SS in Figure 4. is driven by an external logic, a minimum of 2.75V logic is recommended to allow the maximum ITH range. 300 250 IPRG = HIGH TAGE (mV) 200 IPRG = FLOAT 150 IPRG = LOW 100 50 MAXIMUM CURRENT SENSE VOL 0 1 20 40 60 80 100 DUTY CYCLE (%) 3873 F04
Figure 4. Maximum SENSE Threshold Voltage vs Duty Cycle
3873fb 8 For more information www.linear.com/LTC3873
OPERATION
(nominally 8.4V) at least momentarily to enable LTC3873
Light Load Operation
operation. The VCC voltage is then allowed to fall to VTURNOFF Under very light load current conditions, the I (nominally 4V) before undervoltage lockout disables the TH pin volt- age will be very close to the zero current level of 0.85V. LTC3873. This wide UVLO hysteresis range supports the As the load current decreases further, an internal offset at use of trickle charger on the flyback transformer to power the current comparator input will assure that the current the LTC3873—see the section, VCC Bias Power. The RUN/SS comparator remains tripped (even at zero load current) and pin can be driven below VSHDN (nominally 0.7V) to force the regulator will start to skip cycles in order to maintain the LTC3873 into shutdwn. When the chip is off, the input regulation. This behavior allows the regulator to maintain supply current is typically only 55μA. constant frequency down to very light loads, resulting in low
Soft-Start
output ripple as well as low audible noise and reduced RF Leave the RUN/SS pin open to use the internal 3.3ms interference while providing high light load efficiency. soft-start. During the internal soft-start, a voltage ramp
Current Sense
limits the VITH. 3.3ms is required for ITH to ramp from zero current level to full current level. The soft-start can During the switch on-time, the control circuit limits the be lengthened by placing an external capacitor from the maximum voltage drop across the current sense com- RUN/SS pin to the GND. A 3μA current will charge the ponent to about 295mV, 110mV and 185mV at low duty capacitor, pulling the RUN/SS pin above the shutdown cycle with IPRG tied to VIN, GND or left floating respec- threshold and a 15µA pull-up current will continue to ramp tively. It is reduced with increasing duty cycle as shown RUN/SS to limit VITH during the start-up. When RUN/SS in Figure 4. is driven by an external logic, a minimum of 2.75V logic is recommended to allow the maximum ITH range. 300 250 IPRG = HIGH TAGE (mV) 200 IPRG = FLOAT 150 IPRG = LOW 100 50 MAXIMUM CURRENT SENSE VOL 0 1 20 40 60 80 100 DUTY CYCLE (%) 3873 F04
Figure 4. Maximum SENSE Threshold Voltage vs Duty Cycle
3873fb 8 For more information www.linear.com/LTC3873