Datasheet LT3837 (Analog Devices) - 6

LT3837
TYPICAL PERFORMANCE CHARACTERISTICS PG Delay Time vs Temperature Enable Delay Time vs Temperature
300 320 RENDLY = 90k 250 300 RPGDLY = 27.4k 200 280 (ns) 150 (ns) 260 t ED t PGDLY RPGDLY = 16.9k 100 240 50 220 0 200 –50 –25 0 25 50 75 100 125 –50 –25 0 25 50 75 100 125 TEMPERATURE (°C) TEMPERATURE (°C) 3837 G19 3837 G20
PIN FUNCTIONS SG (Pin 1):
Synchronous gate drive output. This pin pro-
SFST (Pin 6):
This pin, in conjunction with a capacitor to vides an output signal for a secondary-side synchronous ground, controls the ramp-up of peak primary current as switch. Large dynamic currents may flow during voltage sensed through the sense resistor. This is used to control transitions. See the Applications Information section for converter inrush current at start-up. The VC pin voltage details. cannot exceed the SFST pin voltage, so as SFST increases,
V
the maximum voltage on VC increases commensurately,
CC (Pin 2):
Supply voltage pin. Bypass this pin to ground with a 4.7µF capacitor or more. allowing higher peak currents. Total VC ramp time is ap- proximately 70ms per µF of capacitance. Leave pin open
tON (Pin 3):
Pin for external programming resistor to set if not using the soft-start function. the minimum time that the primary switch is on for each cycle. Minimum turn-on facilitates the isolated feedback
OSC (Pin 7):
This pin in conjunction with an external method. See the Applications Information section for capacitor defines the controller oscillator frequency. The details. frequency is approximately 100kHz • 100/COSC(pF).
ENDLY (Pin 4):
Pin for external programming resistor to
FB (Pin 8):
Pin for the feedback node for the power supply set enable delay time. The enable delay time disables the feedback amplifier. Feedback is sensed via a transformer feedback amplifier for a fixed time after the turn-off of the winding and enabled during the flyback period. This pin primary-side MOSFET. This allows the leakage inductance also sinks additional current to compensate for load current voltage spike to be ignored for flyback voltage sensing. variation as set by the RCMP pin. Keep the Thevenin equiva- See the Applications Information section for details. lent resistance of the feedback divider at roughly 3k.
SYNC (Pin 5):
Pin for synchronizing the internal oscillator with an external clock. The positive edge on a pulse causes the oscillator to discharge causing PG to go low (off) and SG high (on). The sync threshold is typically 1.53V. See the Applications Information section for details. Tie to ground if unused. 3837fd 6 Document Outline features applications description Typical Application absolute maximum ratings Pin Configuration order information electrical characteristics typical performance characteristics pin functions block diagram flyback feedback amplifier timing diagram operation applications information typical application Package description Revision History related parts