Datasheet LTC3721-1 (Analog Devices) - 10

LTC3721-1
U OPERATIO
VCC should be bypassed with a 0.1µF to 1µF multilayer UVLO is present and greater than 5V prior to the VCC UVLO ceramic capacitor to decouple the fast transient currents circuitry activation, then the internal UVLO logic will demanded by the output drivers and a bulk tantalum or prevent output switching until the following three condi- electrolytic capacitor to hold up the VCC supply before the tions are met: (1) VCC UVLO is enabled, (2) VREF is in bootstrap winding, or an auxiliary regulator circuit takes regulation and (3) UVLO pin is greater than 5V. over. UVLO can also be used to enable and disable the power CHOLDUP = (ICC + IDRIVE) • tDELAY/3.8V converter. An open drain transistor connected to UVLO as (minimum UVLO hysteresis) shown in Figure 3 provides this capability. Regulated bias supplies as low as 7V can be utilized to
Off-Line Bias Supply Generation
provide bias to the LTC3721-1. Refer to Figure 2 for various bias supply configurations. If a regulated bias supply is not available to provide VCC voltage to the LTC3721-1 and supporting circuitry, one
Programming Undervoltage Lockout
must be generated. Since the power requirement is small, The LTC3721-1 provides undervoltage lockout (UVLO) approximately 1W, and the regulation is not critical, a control for the input DC voltage feed to the power con- simple open-loop method is usually the easiest and lowest verter in addition to the V cost approach. One method that works well is to add a CC UVLO function described in the preceding section. Input DC feed UVLO is provided with winding to the main power transformer, and post regulate the UVLO pin. A comparator on UVLO compares a divided the resultant square wave with an L-C filter (see Figure 4a). down input DC feed voltage to the 5V precision reference. The advantage of this approach is that it maintains decent When the 5V level is exceeded on UVLO, the SS pin is regulation as the supply voltage varies, and it does not released and output switching commences. At the same require full safety isolation from the input winding of the time a 10µA current is enabled which flows out of UVLO transformer. Some manufacturers include a primary wind- into the voltage divider connected to UVLO. The amount of ing for this purpose in their standard product offerings as DC feed hysteresis provided by this current is: 10µA • well. A different approach is to add a winding to the output R inductor and peak detect and filter the square wave signal TOP, (Figure 3). The system UVLO threshold is: 5V • {(R (see Figure 4b). The polarity of this winding is designed so TOP + RBOTTOM)/RBOTTOM}. If the voltage applied to VIN VIN VCC 12V ±10% VBIAS < VUVLO RSTART 1N5226 1.5k 1N914 R 3V START + 2k + 15V* CHOLD 1µF 1µF 1µF CHOLD 19211 F04a V V 37211 F02 CC CC *OPTIONAL
Figure 2. Bias Configurations Figure 4a. Auxiliary Winding Bias Supply
VIN VOUT LOUT RTOP RSTART + ISO BARRIER UVLO 1µF C ON OFF R HOLD BOTTOM 19211 F04b 37211 F03 VCC
Figure 3. System UVLO Setup Figure 4b. Output Inductor Bias Supply
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