Datasheet LTC1871 (Analog Devices) - 9

LTC1871
OPERATION
L D reset pulse to the main RS latch. Because this RS latch is V V IN OUT reset-dominant, the power MOSFET is actively held off for VIN + the duration of an output overvoltage condition. SENSE COUT VSW The LTC1871 can be used either by sensing the voltage GATE drop across the power MOSFET or by connecting the GND SENSE pin to a conventional shunt resistor in the source GND of the power MOSFET, as shown in Figure 2. Sensing the
2a. SENSE Pin Connection for
voltage across the power MOSFET maximizes converter
Maximum Efficiency (VSW < 36V)
effi ciency and minimizes the component count, but limits L D the output voltage to the maximum rating for this pin (36V). V V IN OUT By connecting the SENSE pin to a resistor in the source V V SW IN of the power MOSFET, the user is able to program output GATE voltages signifi cantly greater than 36V. + SENSE COUT GND
Programming the Operating Mode
RS 1871 F02 GND For applications where maximizing the effi ciency at very light loads (e.g., <100μA) is a high priority, the current
2b. SENSE Pin Connection for Precise Control of Peak Current or for VSW > 36V
in the output divider could be decreased to a few micro- amps and Burst Mode operation should be applied (i.e.,
Figure 2. Using the SENSE Pin On the LTC1871
the MODE/SYNC pin should be connected to ground). The nominal operating frequency of the LTC1871 is pro- In applications where fi xed frequency operation is more grammed using a resistor from the FREQ pin to ground critical than low current effi ciency, or where the lowest and can be controlled over a 50kHz to 1000kHz range. In output ripple is desired, pulse-skip mode operation should addition, the internal oscillator can be synchronized to be used and the MODE/SYNC pin should be connected an external clock applied to the MODE/SYNC pin and can to the INTVCC pin. This allows discontinuous conduction be locked to a frequency between 100% and 130% of its mode (DCM) operation down to near the limit defi ned nominal value. When the MODE/SYNC pin is left open, it by the chip’s minimum on-time (about 175ns). Below is pulled low by an internal 50k resistor and Burst Mode this output current level, the converter will begin to skip operation is enabled. If this pin is taken above 2V or an cycles in order to maintain output regulation. Figures 3 external clock is applied, Burst Mode operation is disabled and 4 show the light load switching waveforms for Burst and the IC operates in continuous mode. With no load (or Mode and pulse-skip mode operation for the converter an extremely light load), the controller will skip pulses in in Figure 1. order to maintain regulation and prevent excessive output ripple.
Burst Mode Operation
The RUN pin controls whether the IC is enabled or is in a low Burst Mode operation is selected by leaving the MODE/ current shutdown state. A micropower 1.248V reference SYNC pin unconnected or by connecting it to ground. In and comparator C2 allow the user to program the supply normal operation, the range on the ITH pin corresponding to voltage at which the IC turns on and off (comparator C2 no load to full load is 0.30V to 1.2V. In Burst Mode opera- has 100mV of hysteresis for noise immunity). With the tion, if the error amplifi er EA drives the ITH voltage below RUN pin below 1.248V, the chip is off and the input supply 0.525V, the buffered ITH input to the current comparator current is typically only 10μA. C1 will be clamped at 0.525V (which corresponds to 25% of maximum load current). The inductor current peak is An overvoltage comparator OV senses when the FB pin then held at approximately 30mV divided by the power exceeds the reference voltage by 6.5% and provides a 1871fe 9