Datasheet LT1681 (Analog Devices) - 7

LT1681
U U U PI FU CTIO S
voltage on the pin is reduced to 1.5V, the pin becomes high current for start-up. A 10µA current is forced from this pin impedance and the charging cycle repeats. The oscillator onto an external capacitor. As the SS pin voltage ramps operates at twice the switching frequency of the controller. up, so does the LT1681 internally sensed current limit. This effectively forces the internal current limit to ramp Oscillator frequency fOSC can be approximated by the from zero, allowing overall converter current to slowly relation: increase until normal output regulation is achieved. This   – –  1 function reduces output overshoot on converter start-up.  1  R –  2 6 –4   f ≅ 0 5 . •10 + C FSET  8 •10  OSC FSET + +  The soft-start function incorporates a 1V  BE “dead zone” 3  RFSET     such that a zero current condition is maintained on the VC pin until the SS pin rises to 1VBE above ground.
SYNC (Pin 7):
Oscillator Synchronization Input Pin with TTL-Level Compatible Input. The SYNC input signal (at the The SS pin voltage is reset to start-up condition during desired synchronized operating frequency) controls both shutdown, undervoltage lockout and overvoltage or the internal oscillator (running at twice the SYNC fre- overcurrent events, yielding a graceful converter output quency) and the output switch phase. If the synchroniza- recovery from these events. tion function is not desired, this pin may be shorted to
VFB (Pin 9):
Error Amplifier Inverting Input. Typically ground. connected to a resistor divider from the output and com- The LT1681 internal oscillator drives a toggle flip-flop that pensation components to the VC pin. assures ≤ 50% duty cycle operation during oscillator free- The VFB pin is the converter output voltage feedback node. run. The oscillator, therefore, runs at twice the operating Input bias current of ~50nA forces the pin high in the event frequency of the converter. The SYNC input decoder of an open-feedback path condition. The error amplifier is incorporates a frequency doubling circuit for oscillator internally referenced to 1.25V. synchronization, resetting the internal oscillator on both Values for the V the rising and falling edges of the input signal. OUT to VFB feedback resistor (RFB1) and the VFB to ground resistor (RFB2) can be calculated to program The SYNC input decoder also differentiates transition converter output voltage (VOUT) via the following relation: phase and forces the toggle flip-flop to phase-lock with the V SYNC input. A transition to logic high on the SYNC input OUT = 1.25 • (RFB1 + RFB2)/RFB2 signal corresponds to the initiation of a new switching
VC (Pin 10):
Error Amplifier Output. The LT1681 error cycle (primary switches turning on pending current con- amplifier is a low impedance output inverting gain stage. trol) and a transition to logic low forces a primary switch The amplifier has ample current source capability to allow off state. As such, the maximum operating duty cycle is easy integration of isolation optocouplers that require bias equal to the duty cycle of the SYNC signal. The SYNC input currents up to 10mA. External DC loading of the VC pin can therefore be used to reduce the maximum duty cycle reduces the external current sourcing capacity of the of the converter by reducing the duty cycle of the SYNC 5VREF pin by the same amount as the load on the VC pin. input. The error amplifier is typically configured using a feedback
SS (Pin 8):
Soft-Start. Connect a capacitor (CSS) from this RC network to realize an integrator circuit. This circuit pin to ground. creates the dominant pole for the converter regulation feedback loop. Integrator characteristics are dominated The output voltage of the LT1681 error amplifier corre- by the value of the capacitor connected from the V sponds to the peak current sense amplifier output de- C pin to the V tected before resetting the switch outputs. The soft-start FB pin and the feedback resistor connected to the VFB pin. Specific integrator characteristics can be configured circuit forces the error amplifier output to a zero sense to optimize transient response. 1681f 7