Datasheet LTC1922-1 (Analog Devices) - 6
| 制造商 | Analog Devices |
| 描述 | Synchronous Phase Modulated Full-Bridge Controller |
| 页数 / 页 | 24 / 6 — PIN FUNCTIONS. SYNC (Pin 1):. VREF (Pin 11):. RAMP (Pin 2):. OUTF (Pin … |
| 文件格式/大小 | PDF / 316 Kb |
| 文件语言 | 英语 |
PIN FUNCTIONS. SYNC (Pin 1):. VREF (Pin 11):. RAMP (Pin 2):. OUTF (Pin 12):. CS (Pin 3):. OUTE (Pin 13):. COMP (Pin 4):. OUTD (Pin 14):
该数据表的模型线
文件文字版本
LTC1922-1
U U U PIN FUNCTIONS SYNC (Pin 1):
Synchronization Input/Output for the
VREF (Pin 11):
5V Reference Output. VREF is capable of Oscillator. Terminate SYNC with a 5.1k resistor to GND. supplying up to 15mA to external circuitry. Bypass VREF with a 1µF (minimum) ceramic capacitor to GND.
RAMP (Pin 2):
Input to Phase Modulator Comparator. The voltage on RAMP is internally level shifted by 400mV.
OUTF (Pin 12):
50mA Driver Output for Secondary Side Current Doubler Synchronous Rectifier.
CS (Pin 3):
Input to Current Limit Comparators, Output of Slope Compensation Circuitry.
OUTE (Pin 13):
50mA Driver Output for Secondary Side Current Doubler Synchronous Rectifier.
COMP (Pin 4):
Error Amplifier Output, Input to Phase Modulator.
OUTD (Pin 14):
50mA Driver Output for Active Leg Low Side.
RLEB (Pin 5):
Timing Resistor for Leading Edge Blanking. Use a 10k to 100k resistor to program from 40ns to 310ns
VCC (Pin 15):
Chip Power Supply Input, 10.3V Shunt of leading edge blanking. A ±1% tolerance resistor is Regulator. Bypass VCC with a 0.1µF or larger ceramic recommended. Leading edge blanking may be defeated by capacitor to GND. connecting RLEB to VREF.
OUTC (Pin 16):
50mA Driver Output for Active Leg High
FB (Pin 6):
Error Amplifier Inverting Input. This is the Side. voltage feedback input for the LTC1922-1.
OUTB (Pin 17):
50mA Driver Output for Passive Leg Low
SS (Pin 7):
Soft-Start/Restart Delay Circuitry Timing Side. Capacitor.
OUTA (Pin 18):
50mA Driver Output for Passive Leg High
PDLY (Pin 8):
Passive Leg Delay Circuit Input. Side.
SBUS (Pin 9):
Input (Bus) Voltage Sensing Input.
GND (Pin 19):
All Voltages on the LTC1922-1 Are Referred to GND.
ADLY (Pin 10):
Active Leg Delay Circuit Input.
CT (Pin 20):
Timing Capacitor for Oscillator. Use ±5% or better multilayer NPO ceramic for best results. 6
U U U PIN FUNCTIONS SYNC (Pin 1):
Synchronization Input/Output for the
VREF (Pin 11):
5V Reference Output. VREF is capable of Oscillator. Terminate SYNC with a 5.1k resistor to GND. supplying up to 15mA to external circuitry. Bypass VREF with a 1µF (minimum) ceramic capacitor to GND.
RAMP (Pin 2):
Input to Phase Modulator Comparator. The voltage on RAMP is internally level shifted by 400mV.
OUTF (Pin 12):
50mA Driver Output for Secondary Side Current Doubler Synchronous Rectifier.
CS (Pin 3):
Input to Current Limit Comparators, Output of Slope Compensation Circuitry.
OUTE (Pin 13):
50mA Driver Output for Secondary Side Current Doubler Synchronous Rectifier.
COMP (Pin 4):
Error Amplifier Output, Input to Phase Modulator.
OUTD (Pin 14):
50mA Driver Output for Active Leg Low Side.
RLEB (Pin 5):
Timing Resistor for Leading Edge Blanking. Use a 10k to 100k resistor to program from 40ns to 310ns
VCC (Pin 15):
Chip Power Supply Input, 10.3V Shunt of leading edge blanking. A ±1% tolerance resistor is Regulator. Bypass VCC with a 0.1µF or larger ceramic recommended. Leading edge blanking may be defeated by capacitor to GND. connecting RLEB to VREF.
OUTC (Pin 16):
50mA Driver Output for Active Leg High
FB (Pin 6):
Error Amplifier Inverting Input. This is the Side. voltage feedback input for the LTC1922-1.
OUTB (Pin 17):
50mA Driver Output for Passive Leg Low
SS (Pin 7):
Soft-Start/Restart Delay Circuitry Timing Side. Capacitor.
OUTA (Pin 18):
50mA Driver Output for Passive Leg High
PDLY (Pin 8):
Passive Leg Delay Circuit Input. Side.
SBUS (Pin 9):
Input (Bus) Voltage Sensing Input.
GND (Pin 19):
All Voltages on the LTC1922-1 Are Referred to GND.
ADLY (Pin 10):
Active Leg Delay Circuit Input.
CT (Pin 20):
Timing Capacitor for Oscillator. Use ±5% or better multilayer NPO ceramic for best results. 6