Datasheet LTC3900 (Analog Devices) - 8

LTC3900
applicaTions inForMaTion
The timer circuit and current sense comparator in LTC3900 designed to be of the same magnitude (1.4V typical) but are used to prevent reverse current buildup in the output opposite in polarity. In some situations, for example dur- inductor. ing power up or power down, the SYNC pulse magnitude may be low, slightly higher or lower than the threshold of
Timer
the comparators. This can cause only one of the SYNC Figure 3 shows the LTC3900 timer internal and external comparators to trip. This also appears as incorrect SYNC circuits. The timer operates by using an external R-C pulse and the timer will not reset. charging network to program the time-out period. On The timeout period is determined by the external RTMR every negative transition at the SYNC input, the chip and CTMR values and is independent of the VCC voltage. generates a 200ns pulse to reset the timer cap. If the This is achieved by making the timeout threshold a ratio SYNC signal is missing or incorrect, allowing the timer of VCC. The ratio is 0.2x, set internally by R1 and R2 (see cap voltage to go high, it shuts off both drivers once the Figure 3). The timeout period should be programmed to voltage reaches the time-out threshold. Figure 4 shows be around one period of the primary switching frequency the timer waveforms. using the following formula: A typical forward converter cycle always turns on Q3 TIMEOUT = 0.2 • RTMR • CTMR + 0.27E-6 and Q4 alternately and the SYNC input should alternate To reduce error in the timeout setting due to the discharge between positive and negative pulses. The LTC3900 timer time, select CTMR between 100pF and 1000pF. Start with a also includes sequential logic to monitor the SYNC input CTMR around 470pF and then calculate the required RTMR. sequence. If after one negative pulse, the SYNC compara- CTMR should be placed as close as possible to the LTC3900 tor receives another negative pulse, the LTC3900 will not with minimum PCB trace between CTMR, the TIMER pin reset the timer cap. If no positive SYNC pulse appears, and GND. This is to reduce any ringing caused by the PCB both drivers are shut off once the timer times out. Once trace inductance when CTMR discharges. This ringing may positive pulses reappear the timer resets and the drivers introduce error to the timeout setting. start switching again. This is to protect the external com- ponents in situations where only negative SYNC pulse is The timer input also includes a current sinking clamp present and FG output remains high. Figure 5 shows the circuit (ZTMR in Figure 3) that clamps this pin to about timer waveforms with incorrect SYNC pulses. 0.5 • VCC if there is missing SYNC/timer reset pulse. This clamp circuit prevents the timer cap from getting fully The LTC3900 has two separate SYNC comparators (S+ and charged up to the rail, which results in a longer discharge S– in the Block Diagram) to detect the positive and negative pulses. The threshold voltages of both comparators are SG V SYNC CC R2 R1 LAST 4 PULSE FG TMR RTMR TIMEOUT 7 CG TIMER TIMER RESET ZTMR CTMR RESET (INTERNAL) 3900 F03 TIMER TIMEOUT THRESHOLD
Figure 3. Timer Circuit
3900 F04
Figure 4. Timer Waveforms
3900fb 8 Document Outline Features Description Applications Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Applications Information Typical Applications Package Description Revision History Typical Application Related Parts