Datasheet LTC3901 (Analog Devices) - 8

LTC3901
U U W U APPLICATIO S I FOR ATIO
The timeout period is determined predominantly by the polarity. In some situations, for example during power-up external R or power-down, the SYNC pulse magnitude may be low TMR and CTMR values and is independent of the V (slightly higher or lower than the threshold of the compara- CC voltage. This independence is achieved by making the timeout threshold a ratio of V tors). This can cause only one of the SYNC comparators to CC. The ratio is 0.2x, set internally by R1 and R2 (see Figure 3). The Timeout period trip. This also appears as a double pulse to the sequential should be programmed to around 1 period of the primary logic and both drivers will be shut off. switching frequency using the following formula:
Current Sense
TIMEOUT = 0.2 • RTMR • CTMR + 0.27E-06 The differential input current sense comparators, ISE and To reduce error in the timeout setting due to the discharge ISF (Figure 6), are used for sensing the voltage across the time, select CTMR between 100pF and 1000pF. Start with drain-to-source terminal of the MOSFET through the CSX+ a CTMR around 470pF and then calculate the required and CSX– pins. There are two sets of comparator inputs, RTMR. CTMR should be placed as close as possible to the one for each MOSFET (ME and MF). If the inductor current LTC3901 with minimum PCB trace between CTMR, the reverses into the MOSFET causing CSX+ to rise above TIMER pin and GND. This is to reduce any ringing caused CSX– by more than 10.5mV, the LTC3901 turns off the by the PCB trace inductance when CTMR discharges. This respective MOSFET. This comparator is used to prevent ringing may introduce error to the timeout setting. inductor reverse current buildup during power-down or The timer input also includes a current sinking clamp Burst Mode operation, which may cause damage to the circuit (Z MOSFETs. The 10.5mV input threshold has a positive TMR in Figure 3) that clamps this pin to about 0.5 • V temperature coefficient, which closely matches the TC of CC if there is missing SYNC/timer reset pulse. This clamp circuit prevents the timer capacitor from getting the external MOSFET RDS(ON). The current sense com- fully charged up to the rail, which would result in a longer parator is only active 250ns after the respective driver discharge time. The current sinking capability of the circuit SECOND NEGATIVE SYNC PULSE, is around 1mA. BOTH ME AND MF PULL LOW The timeout function can be disabled by connecting the SYNC 0V timer pin to GND. ME
Synchronization Sequence
A typical push-pull converter cycle always turns off ME MF 3901 F05 and MF alternately. The SYNC input should alternate EXPECTED POSITIVE SYNC PULSE, MF PULLS HIGH between a positive and negative pulse. The LTC3901 includes a sequential logic to monitor the SYNC input
Figure 5. SYNC Double Pulse Operation
pulses. If after one positive pulse the SYNC comparator receives another positive pulse, the LTC3901 sequential T1 RCSE2 logic shuts off both drivers until a negative pulse appears. RCSE1 CSE+ ISE 6 The same applies to double negative pulses; the driver will ME 10.5mV turn on only after receiving a positive pulse. This is to CSE– ZCSE 5 – + 11V protect the external components in situations where only RCSE3 one polarity of the SYNC pulse is present and the corre- LTC3901 sponding driver remains on. Figure 5 shows the SYNC RCSF1 CSF+ ISF 11 double pulse operation. MF 10.5mV The LTC3901 has two separate SYNC comparators (S+ and CSF– ZCSF 12 – + 11V S– in the Block Diagram) to detect the positive and nega- RCSF3 RCSF2 tive pulses. The threshold voltages of both comparators 3901 F06 are designed to be of the same magnitude but opposite in
Figure 6. Current Sense Circuit
3901f 8