Datasheet ATmega8515, ATmega8515L (Atmel) - 9

ATmega8515(L)
Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing – enabling efficient address calculations. One of the these address pointers can also be used as an address pointer for look up tables in Flash Pro- gram memory. These added function registers are the 16-bit X-, Y-, and Z-register, described later in this section. The ALU supports arithmetic and logic operations between registers or between a con- stant and a register. Single register operations can also be executed in the ALU. After an arithmetic operation, the Status Register is updated to reflect information about the result of the operation. Program flow is provided by conditional and unconditional jump and call instructions, able to directly address the whole address space. Most AVR instructions have a single 16-bit word format. Every Program memory address contains a 16- or 32-bit instruction. Program Flash memory space is divided in two sections, the Boot Program section and the Application Program section. Both sections have dedicated Lock bits for write and read/write protection. The SPM instruction that writes into the Application Flash memory section must reside in the Boot Program section. During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the Stack. The Stack is effectively allocated in the general data SRAM, and consequently the Stack size is only limited by the total SRAM size and the usage of the SRAM. All user programs must initialize the SP in the reset routine (before subroutines or interrupts are executed). The Stack Pointer SP is read/write accessible in the I/O space. The data SRAM can easily be accessed through the five different addressing modes supported in the AVR architecture. The memory spaces in the AVR architecture are all linear and regular memory maps. A flexible interrupt module has its Control Registers in the I/O space with an additional Global Interrupt Enable bit in the Status Register. All interrupts have a separate interrupt vector in the Interrupt Vector table. The interrupts have priority in accordance with their Interrupt Vector position. The lower the Interrupt Vector address, the higher the priority. The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers, SPI, and other I/O functions. The I/O Memory can be accessed directly, or as the Data Space locations following those of the Register File, $20 - $5F.
ALU – Arithmetic Logic
The high-performance AVR ALU operates in direct connection with all the 32 general
Unit
purpose working registers. Within a single clock cycle, arithmetic operations between general purpose registers or between a register and an immediate are executed. The ALU operations are divided into three main categories – arithmetic, logical, and bit-func- tions. Some implementations of the architecture also provide a powerful multiplier supporting both signed/unsigned multiplication and fractional format. See the “Instruc- tion Set” section for a detailed description.
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2512K–AVR–01/10 Document Outline Features Pin Configurations Overview Block Diagram Disclaimer AT90S4414/8515 and ATmega8515 Compatibility AT90S4414/8515 Compatibility Mode Pin Descriptions VCC GND Port A (PA7..PA0) Port B (PB7..PB0) Port C (PC7..PC0) Port D (PD7..PD0) Port E(PE2..PE0) RESET XTAL1 XTAL2 Resources About Code Examples AVR CPU Core Introduction Architectural Overview ALU – Arithmetic Logic Unit Status Register General Purpose Register File The X-register, Y-register, and Z-register Stack Pointer Instruction Execution Timing Reset and Interrupt Handling Interrupt Response Time AVR ATmega8515 Memories In-System Reprogrammable Flash Program memory SRAM Data Memory Data Memory Access Times EEPROM Data Memory EEPROM Read/Write Access The EEPROM Address Register – EEARH and EEARL The EEPROM Data Register – EEDR The EEPROM Control Register – EECR EEPROM Write During Power- down Sleep Mode Preventing EEPROM Corruption I/O Memory External Memory Interface Overview Using the External Memory Interface Address Latch Requirements Pull-up and Bus Keeper Timing XMEM Register Description MCU Control Register – MCUCR Extended MCU Control Register – EMCUCR Special Function IO Register – SFIOR Using all Locations of External Memory Smaller than 64 KB Using all 64KB Locations of External Memory System Clock and Clock Options Clock Systems and their Distribution CPU Clock – clkCPU I/O Clock – clkI/O Flash Clock – clkFLASH Clock Sources Default Clock Source Crystal Oscillator Low-frequency Crystal Oscillator External RC Oscillator Calibrated Internal RC Oscillator Oscillator Calibration Register – OSCCAL External Clock Power Management and Sleep Modes MCU Control Register – MCUCR MCU Control and Status Register – MCUCSR Extended MCU Control Register – EMCUCR Idle Mode Power-down Mode Standby Mode Minimizing Power Consumption Analog Comparator Brown-out Detector Internal Voltage Reference Watchdog Timer Port Pins System Control and Reset Resetting the AVR Reset Sources Power-on Reset External Reset Brown-out Detection Watchdog Reset MCU Control and Status Register – MCUCSR Internal Voltage Reference Voltage Reference Enable Signals and Start-up Time Watchdog Timer Watchdog Timer Control Register – WDTCR Timed Sequences for Changing the Configuration of the Watchdog Timer Safety Level 0 Safety Level 1 Safety Level 2 Interrupts Interrupt Vectors in ATmega8515 Moving Interrupts between Application and Boot Space General Interrupt Control Register – GICR I/O Ports Introduction Ports as General Digital I/O Configuring the Pin Reading the Pin Value Digital Input Enable and Sleep Modes Unconnected pins Alternate Port Functions Special Function IO Register – SFIOR Alternate Functions of Port A Alternate Functions Of Port B Alternate Functions of Port C Alternate Functions of Port D Alternate Functions of Port E Register Description for I/O Ports Port A Data Register – PORTA Port A Data Direction Register – DDRA Port A Input Pins Address – PINA Port B Data Register – PORTB Port B Data Direction Register – DDRB Port B Input Pins Address – PINB Port C Data Register – PORTC Port C Data Direction Register – DDRC Port C Input Pins Address – PINC Port D Data Register – PORTD Port D Data Direction Register – DDRD Port D Input Pins Address – PIND Port E Data Register – PORTE Port E Data Direction Register – DDRE Port E Input Pins Address – PINE External Interrupts MCU Control Register – MCUCR Extended MCU Control Register – EMCUCR General Interrupt Control Register – GICR General Interrupt Flag Register – GIFR 8-bit Timer/Counter0 with PWM Overview Registers Definitions Timer/Counter Clock Sources Counter Unit Output Compare Unit Force Output Compare Compare Match Blocking by TCNT0 Write Using the Output Compare Unit Compare Match Output Unit Compare Output Mode and Waveform Generation Modes of Operation Normal Mode Clear Timer on Compare Match (CTC) Mode Fast PWM Mode Phase Correct PWM Mode Timer/Counter Timing Diagrams 8-bit Timer/Counter Register Description Timer/Counter Control Register – TCCR0 Timer/Counter Register – TCNT0 Output Compare Register – OCR0 Timer/Counter Interrupt Mask Register – TIMSK Timer/Counter Interrupt Flag Register – TIFR Timer/Counter0 and Timer/Counter1 Prescalers Internal Clock Source Prescaler Reset External Clock Source Special Function IO Register – SFIOR 16-bit Timer/Counter1 Overview Registers Definitions Compatibility Accessing 16-bit Registers Reusing the Temporary High Byte Register Timer/Counter Clock Sources Counter Unit Input Capture Unit Input Capture Trigger Source Noise Canceler Using the Input Capture Unit Output Compare Units Force Output Compare Compare Match Blocking by TCNT1 Write Using the Output Compare Unit Compare Match Output Unit Compare Output Mode and Waveform Generation Modes of Operation Normal Mode Clear Timer on Compare Match (CTC) Mode Fast PWM Mode Phase Correct PWM Mode Phase and Frequency Correct PWM Mode Timer/Counter Timing Diagrams 16-bit Timer/Counter Register Description Timer/Counter1 Control Register A – TCCR1A Timer/Counter1 Control Register B – TCCR1B Timer/Counter1 – TCNT1H and TCNT1L Output Compare Register 1 A – OCR1AH and OCR1AL Output Compare Register 1 B – OCR1BH and OCR1BL Input Capture Register 1 – ICR1H and ICR1L Timer/Counter Interrupt Mask Register – TIMSK(1) Timer/Counter Interrupt Flag Register – TIFR(1) Serial Peripheral Interface – SPI SS Pin Functionality Slave Mode Master Mode SPI Control Register – SPCR SPI Status Register – SPSR SPI Data Register – SPDR Data Modes USART Single USART AVR USART vs. AVR UART – Compatibility Clock Generation Internal Clock Generation – The Baud Rate Generator Double Speed Operation (U2X) External Clock Synchronous Clock Operation Frame Formats Parity Bit Calculation USART Initialization Data Transmission – The USART Transmitter Sending Frames with 5 to 8 Data Bits Sending Frames with 9 Data Bits Transmitter Flags and Interrupts Parity Generator Disabling the Transmitter Data Reception – The USART Receiver Receiving Frames with 5 to 8 Data Bits Receiving Frames with 9 Data Bits Receive Compete Flag and Interrupt Receiver Error Flags Parity Checker Disabling the Receiver Flushing the Receive Buffer Asynchronous Data Reception Asynchronous Clock Recovery Asynchronous Data Recovery Asynchronous Operational Range Multi-processor Communication Mode Using MPCM Accessing UBRRH/UCSRC Registers Write Access Read Access USART Register Description USART I/O Data Register – UDR USART Control and Status Register A – UCSRA USART Control and Status Register B – UCSRB USART Control and Status Register C – UCSRC USART Baud Rate Registers – UBRRL and UBRRH Examples of Baud Rate Setting Analog Comparator Analog Comparator Control and Status Register – ACSR Boot Loader Support – Read-While-Write Self-Programming Features Application and Boot Loader Flash Sections Application Section BLS – Boot Loader Section Read-While-Write and No Read-While-Write Flash Sections RWW – Read-While-Write Section NRWW – No Read-While-Write Section Boot Loader Lock bits Entering the Boot Loader Program Store Program memory Control Register – SPMCR Addressing the Flash During Self- Programming Self-Programming the Flash Performing Page Erase by SPM Filling the Temporary Buffer (page loading) Performing a Page Write Using the SPM Interrupt Consideration While Updating BLS Prevent Reading the RWW Section During Self- Programming Setting the Boot Loader Lock bits by SPM EEPROM Write Prevents Writing to SPMCR Reading the Fuse and Lock bits from Software Preventing Flash Corruption Programming Time for Flash when using SPM Simple Assembly Code Example for a Boot Loader ATmega8515 Boot Loader Parameters Memory Programming Program and Data Memory Lock bits Fuse bits Latching of Fuses Signature Bytes Calibration Byte Parallel Programming Parameters, Pin Mapping, and Commands Signal Names Parallel Programming Enter Programming Mode Considerations for Efficient Programming Chip Erase Programming the Flash Programming the EEPROM Reading the Flash Reading the EEPROM Programming the Fuse Low Bits Programming the Fuse High Bits Programming the Lock bits Reading the Fuse and Lock bits Reading the Signature Bytes Reading the Calibration Byte Parallel Programming Characteristics Serial Downloading Serial Programming Pin Mapping Serial Programming Algorithm Data Polling Flash Data Polling EEPROM Electrical Characteristics Absolute Maximum Ratings* External Clock Drive Waveforms External Clock Drive SPI Timing Characteristics External Data Memory Timing ATmega8515 Typical Characteristics Active Supply Current Idle Supply Current Power-Down Supply Current Standby Supply Current Pin Pull-up Pin Driver Strength Pin Thresholds And Hysteresis BOD Thresholds And Analog Comparator Offset Internal Oscillator Speed Current Consumption Of Peripheral Units Current Consumption In Reset And Reset Pulsewidth Register Summary Instruction Set Summary Ordering Information Packaging Information 44A 40P6 44J 44M1 Errata ATmega8515(L) Rev. C and D Datasheet Revision History Changes from Rev. 2512J-10/06 to Rev. 2512K-01/10 Changes from Rev. 2512I-08/06 to Rev. 2512J-10/06 Changes from Rev. 2512H-04/06 to Rev. 2512I-08/06 Changes from Rev. 2512G-03/05 to Rev. 2512H-04/06 Changes from Rev. 2512F-12/03 to Rev. 2512G-03/05 Rev. 2512E-09/03 Rev. 2512E-09/03 Rev. 2512D-02/03 Rev. 2512C-10/02 Rev. 2512B-09/02 Rev. 2512A-04/02 Table of Contents