Datasheet AT90PWM1 (Atmel) - 10

The fast-access Register File contains 32 x 8-bit general purpose working registers with a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typ- ical ALU operation, two operands are output from the Register File, the operation is executed, and the result is stored back in the Register File – in one clock cycle. Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing – enabling efficient address calculations. One of the these address pointers can also be used as an address pointer for look up tables in Flash program memory. These added function registers are the 16-bit X-, Y-, and Z-register, described later in this section. The ALU supports arithmetic and logic operations between registers or between a constant and a register. Single register operations can also be executed in the ALU. After an arithmetic opera- tion, the Status Register is updated to reflect information about the result of the operation. Program flow is provided by conditional and unconditional jump and call instructions, able to directly address the whole address space. Most AVR instructions have a single 16-bit word for- mat. Every program memory address contains a 16- or 32-bit instruction. Program Flash memory space is divided in two sections, the Boot Program section and the Application Program section. Both sections have dedicated Lock bits for write and read/write protection. The SPM (Store Program Memory) instruction that writes into the Application Flash memory section must reside in the Boot Program section. During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the Stack. The Stack is effectively allocated in the general data SRAM, and consequently the Stack size is only limited by the total SRAM size and the usage of the SRAM. All user programs must initialize the SP in the Reset routine (before subroutines or interrupts are executed). The Stack Pointer (SP) is read/write accessible in the I/O space. The data SRAM can easily be accessed through the five different addressing modes supported in the AVR architecture. The memory spaces in the AVR architecture are all linear and regular memory maps. A flexible interrupt module has its control registers in the I/O space with an additional Global Interrupt Enable bit in the Status Register. All interrupts have a separate Interrupt Vector in the Interrupt Vector table. The interrupts have priority in accordance with their Interrupt Vector posi- tion. The lower the Interrupt Vector address, the higher is the priority. The I/O memory space contains 64 addresses for CPU peripheral functions as Control Regis- ters, SPI, and other I/O functions. The I/O Memory can be accessed directly, or as the Data Space locations following those of the Register File, 0x20 - 0x5F. In addition, the AT90PWM1 has Extended I/O space from 0x60 - 0xFF in SRAM where only the ST/STS/STD and LD/LDS/LDD instructions can be used.
5.3 ALU – Arithmetic Logic Unit
The high-performance AVR ALU operates in direct connection with all the 32 general purpose working registers. Within a single clock cycle, arithmetic operations between general purpose registers or between a register and an immediate are executed. The ALU operations are divided into three main categories – arithmetic, logical, and bit-functions. Some implementations of the architecture also provide a powerful multiplier supporting both signed/unsigned multiplication and fractional format. See the “Instruction Set” section for a detailed description.
10 AT90PWM1
4378C–AVR–09/08 Document Outline Features 1. History 2. Disclaimer 3. Pin Configurations 3.1 Pin Descriptions 4. Overview 4.1 Block Diagram 4.2 Pin Descriptions 4.2.1 VCC 4.2.2 GND 4.2.3 Port B (PB7..PB0) 4.2.4 Port D (PD7..PD0) 4.2.5 Port E (PE2..0) RESET/ XTAL1/ XTAL2 4.2.6 AVCC 4.2.7 AREF 4.3 About Code Examples 5. AVR CPU Core 5.1 Introduction 5.2 Architectural Overview 5.3 ALU - Arithmetic Logic Unit 5.4 Status Register 5.5 General Purpose Register File 5.5.1 The X-register, Y-register, and Z-register 5.6 Stack Pointer 5.7 Instruction Execution Timing 5.8 Reset and Interrupt Handling 5.8.1 Interrupt Behavior 5.8.2 Interrupt Response Time 6. Memories 6.1 In-System Reprogrammable Flash Program Memory 6.2 SRAM Data Memory 6.2.1 SRAM Data Access Times 6.3 EEPROM Data Memory 6.3.1 EEPROM Read/Write Access 6.3.2 The EEPROM Address Registers - EEARH and EEARL 6.3.3 The EEPROM Data Register - EEDR 6.3.4 The EEPROM Control Register - EECR 6.3.5 Preventing EEPROM Corruption 6.4 I/O Memory 6.5 General Purpose I/O Registers 6.5.1 General Purpose I/O Register 0 - GPIOR0 6.5.2 General Purpose I/O Register 1 - GPIOR1 6.5.3 General Purpose I/O Register 2 - GPIOR2 6.5.4 General Purpose I/O Register 3- GPIOR3 7. System Clock 7.1 Clock Systems and their Distribution 7.1.1 CPU Clock - clkCPU 7.1.2 I/O Clock - clkI/O 7.1.3 Flash Clock - clkFLASH 7.1.4 PLL Clock - clkPLL 7.1.5 ADC Clock - clkADC 7.2 Clock Sources 7.3 Default Clock Source 7.4 Low Power Crystal Oscillator 7.5 Calibrated Internal RC Oscillator 7.6 PLL 7.6.1 Internal PLL for PSC 7.6.2 PLL Control and Status Register - PLLCSR 7.7 128 kHz Internal Oscillator 7.8 External Clock 7.9 Clock Output Buffer 7.10 System Clock Prescaler 7.10.1 Clock Prescaler Register - CLKPR 8. Power Management and Sleep Modes 8.0.1 Sleep Mode Control Register - SMCR 8.1 Idle Mode 8.2 ADC Noise Reduction Mode 8.3 Power-down Mode 8.4 Standby Mode 8.5 Power Reduction Register 8.5.1 Power Reduction Register - PRR 8.6 Minimizing Power Consumption 8.6.1 Analog to Digital Converter 8.6.2 Analog Comparator 8.6.3 Brown-out Detector 8.6.4 Internal Voltage Reference 8.6.5 Watchdog Timer 8.6.6 Port Pins 8.6.7 On-chip Debug System 9. System Control and Reset 9.0.1 Resetting the AVR 9.0.2 Reset Sources 9.0.3 Power-on Reset 9.0.4 External Reset 9.0.5 Brown-out Detection 9.0.6 Watchdog Reset 9.0.7 MCU Status Register - MCUSR 9.1 Internal Voltage Reference 9.1.1 Voltage Reference Enable Signals and Start-up Time 9.1.2 Voltage Reference Characteristics 9.2 Watchdog Timer 9.2.1 Watchdog Timer Control Register - WDTCSR 10. Interrupts 10.1 Interrupt Vectors in AT90PWM1 10.1.1 Moving Interrupts Between Application and Boot Space 10.1.2 MCU Control Register - MCUCR 11. I/O-Ports 11.1 Introduction 11.2 Ports as General Digital I/O 11.2.1 Configuring the Pin 11.2.2 Toggling the Pin 11.2.3 Switching Between Input and Output 11.2.4 Reading the Pin Value 11.2.5 Digital Input Enable and Sleep Modes 11.3 Alternate Port Functions 11.3.1 MCU Control Register - MCUCR 11.3.2 Alternate Functions of Port B 11.3.3 Alternate Functions of Port D 11.3.4 Alternate Functions of Port E 11.4 Register Description for I/O-Ports 11.4.1 Port B Data Register - PORTB 11.4.2 Port B Data Direction Register - DDRB 11.4.3 Port B Input Pins Address - PINB 11.4.4 Port D Data Register - PORTD 11.4.5 Port D Data Direction Register - DDRD 11.4.6 Port D Input Pins Address - PIND 11.4.7 Port E Data Register - PORTE 11.4.8 Port E Data Direction Register - DDRE 11.4.9 Port E Input Pins Address - PINE 12. External Interrupts 12.0.1 External Interrupt Control Register A - EICRA 12.0.2 External Interrupt Mask Register - EIMSK 12.0.3 External Interrupt Flag Register - EIFR 13. Timer/Counter0 and Timer/Counter1 Prescalers 13.0.1 Internal Clock Source 13.0.2 Prescaler Reset 13.0.3 External Clock Source 13.0.4 General Timer/Counter Control Register - GTCCR 14. 8-bit Timer/Counter0 with PWM 14.1 Overview 14.1.1 Definitions 14.1.2 Registers 14.2 Timer/Counter Clock Sources 14.3 Counter Unit 14.4 Output Compare Unit 14.4.1 Force Output Compare 14.4.2 Compare Match Blocking by TCNT0 Write 14.4.3 Using the Output Compare Unit 14.5 Compare Match Output Unit 14.5.1 Compare Output Mode and Waveform Generation 14.6 Modes of Operation 14.6.1 Normal Mode 14.6.2 Clear Timer on Compare Match (CTC) Mode 14.6.3 Fast PWM Mode 14.6.4 Phase Correct PWM Mode 14.7 Timer/Counter Timing Diagrams 14.8 8-bit Timer/Counter Register Description 14.8.1 Timer/Counter Control Register A - TCCR0A 14.8.2 Timer/Counter Control Register B - TCCR0B 14.8.3 Timer/Counter Register - TCNT0 14.8.4 Output Compare Register A - OCR0A 14.8.5 Output Compare Register B - OCR0B 14.8.6 Timer/Counter Interrupt Mask Register - TIMSK0 14.8.7 Timer/Counter 0 Interrupt Flag Register - TIFR0 15. 16-bit Timer/Counter1 with PWM 15.1 Overview 15.1.1 Registers 15.1.2 Definitions 15.2 Accessing 16-bit Registers 15.2.1 Reusing the Temporary High Byte Register 15.3 Timer/Counter Clock Sources 15.4 Counter Unit 15.5 Input Capture Unit 15.5.1 Input Capture Trigger Source 15.5.2 Noise Canceler 15.5.3 Using the Input Capture Unit 15.6 Output Compare Units 15.6.1 Force Output Compare 15.6.2 Compare Match Blocking by TCNTn Write 15.6.3 Using the Output Compare Unit 15.7 Compare Match Output Unit 15.7.1 Compare Output Mode and Waveform Generation 15.8 Modes of Operation 15.8.1 Normal Mode 15.8.2 Clear Timer on Compare Match (CTC) Mode 15.8.3 Fast PWM Mode 15.8.4 Phase Correct PWM Mode 15.8.5 Phase and Frequency Correct PWM Mode 15.9 Timer/Counter Timing Diagrams 15.10 16-bit Timer/Counter Register Description 15.10.1 Timer/Counter1 Control Register A - TCCR1A 15.10.2 Timer/Counter1 Control Register B - TCCR1B 15.10.3 Timer/Counter1 Control Register C - TCCR1C 15.10.4 Timer/Counter1 - TCNT1H and TCNT1L 15.10.5 Output Compare Register 1 A - OCR1AH and OCR1AL 15.10.6 Output Compare Register 1 B - OCR1BH and OCR1BL 15.10.7 Input Capture Register 1 - ICR1H and ICR1L 15.10.8 Timer/Counter1 Interrupt Mask Register - TIMSK1 15.10.9 Timer/Counter1 Interrupt Flag Register - TIFR1 16. Power Stage Controller - (PSC0, PSC2) 16.1 Features 16.2 Overview 16.3 PSC Description 16.3.1 PSC2 Distinctive Feature 16.3.2 Output Polarity 16.4 Signal Description 16.4.1 Input Description 16.4.2 Output Description 16.5 Functional Description 16.5.1 Waveform Cycles 16.5.2 Running Mode Description 16.5.2.1 Four Ramp Mode 16.5.2.2 Two Ramp Mode 16.5.2.3 One Ramp Mode 16.5.2.4 Center Aligned Mode 16.5.3 Fifty Percent Waveform Configuration 16.6 Update of Values 16.6.1 Value Update Synchronization 16.7 Enhanced Resolution 16.7.1 Frequency distribution 16.7.2 Modes of Operation 16.7.2.1 Normal Mode 16.7.2.2 Enhanced Mode 16.8 PSC Inputs 16.8.1 PSC Retri gger Behaviour versus PSC running modes 16.8.2 Retrigger PSCOUTn0 On External Event 16.8.3 Retrigger PSCOUTn1 On External Event 16.8.3.1 Burst Generation 16.8.4 PSC Input Configuration 16.8.4.1 Filter Enable 16.8.4.2 Signal Polarity 16.8.4.3 Input Mode Operation 16.9 PSC Input Mode 1: Stop signal, Jump to Opposite Dead-Time and Wait 16.10 PSC Input Mode 2: Stop signal, Execute Opposite Dead-Time and Wait 16.11 PSC Input Mode 3: Stop signal, Execute Opposite while Fault active 16.12 PSC Input Mode 4: Deactivate outputs without changing timing. 16.13 PSC Input Mode 5: Stop signal and Insert Dead-Time 16.14 PSC Input Mode 6: Stop signal, Jump to Opposite Dead-Time and Wait. 16.15 PSC Input Mode 7: Halt PSC and Wait for Software Action 16.16 PSC Input Mode 8: Edge Retrigger PSC 16.17 PSC Input Mode 9: Fixed Frequency Edge Retrigger PSC 16.18 PSC Input Mode 14: Fixed Frequency Edge Retrigger PSC and Disactivate Output 16.18.1 Available Input Mode according to Running Mode 16.18.2 Event Capture 16.18.3 Using the Input Capture Unit 16.19 PSC2 Outputs 16.19.1 Output Matrix 16.19.2 PSCOUT22 & PSCOUT23 Selectors 16.20 Analog Synchronization 16.21 Interrupt Handling 16.22 PSC Synchronization 16.22.1 Fault events in Autorun mode 16.23 PSC Clock Sources 16.24 Interrupts 16.24.1 List of Interrupt Vector 16.24.2 PSC Interrupt Vectors in AT90PWM1 16.25 PSC Register Definition 16.25.1 PSC 0 Synchro and Output Configuration - PSOC0 16.25.2 PSC 2 Synchro and Output Configuration - PSOC2 16.25.3 Output Compare SA Register - OCRnSAH and OCRnSAL 16.25.4 Output Compare RA Register - OCRnRAH and OCRnRAL 16.25.5 Output Compare SB Register - OCRnSBH and OCRnSBL 16.25.6 Output Compare RB Register - OCRnRBH and OCRnRBL 16.25.7 PSC 0 Configuration Register - PCNF0 16.25.8 PSC 1 Configuration Register - PCNF1 16.25.9 PSC 2 Configuration Register - PCNF2 16.25.10 PSC 0 Control Register - PCTL0 16.25.11 PSC 1 Control Register - PCTL1 16.25.12 PSC 2 Control Register - PCTL2 16.25.13 PSC n Input A Control Register - PFRCnA 16.25.14 PSC n Input B Control Register - PFRCnB 16.25.15 PSC 0 Input Capture Register - PICR0H and PICR0L 16.25.16 PSC 2 Input Capture Register - PICR2H and PICR2L 16.26 PSC2 Specific Register 16.26.1 PSC 2 Output Matrix - POM2 16.26.2 PSC0 Interrupt Mask Register - PIM0 16.26.3 PSC2 Interrupt Mask Register - PIM2 16.26.4 PSC0 Interrupt Flag Register - PIFR0 16.26.5 PSC2 Interrupt Flag Register - PIFR2 17. Serial Peripheral Interface - SPI 17.1 Features 17.2 SS Pin Functionality 17.2.1 Slave Mode 17.2.2 Master Mode 17.2.3 MCU Control Register - MCUCR 17.2.4 SPI Control Register - SPCR 17.2.5 SPI Status Register - SPSR 17.2.6 SPI Data Register - SPDR 17.3 Data Modes 18. Analog Comparator 18.1 Overview 18.2 Analog Comparator Register Description 18.2.1 Analog Comparator 0 Control Register - AC0CON 18.2.2 Analog Comparator 2 Control Register - AC2CON 18.2.3 Analog Comparator Status Register - ACSR 18.2.4 Digital Input Disable Register 0 - DIDR0 18.2.5 Digital Input Disable Register 1- DIDR1 19. Analog to Digital Converter - ADC 19.1 Features 19.2 Operation 19.3 Starting a Conversion 19.4 Prescaling and Conversion Timing 19.5 Changing Channel or Reference Selection 19.5.1 ADC Input Channels 19.5.2 ADC Voltage Reference 19.6 ADC Noise Canceler 19.6.1 Analog Input Circuitry 19.6.2 Analog Noise Canceling Techniques 19.6.3 Offset Compensation Schemes 19.6.4 ADC Accuracy Definitions 19.7 ADC Conversion Result 19.8 ADC Register Description 19.8.1 ADC Multiplexer Register - ADMUX 19.8.2 ADC Control and Status Register A - ADCSRA 19.8.3 ADC Control and Status Register B- ADCSRB 19.8.4 ADC Result Data Registers - ADCH and ADCL 19.8.4.1 ADLAR = 0 19.8.4.2 ADLAR = 1 19.8.5 Digital Input Disable Register 0 - DIDR0 19.8.6 Digital Input Disable Register 1- DIDR1 19.9 Amplifier 19.10 Amplifier Control Registers 19.10.1 Amplifier 0 Control and Status register - AMP0CSR 20. debugWIRE On-chip Debug System 20.1 Features 20.2 Overview 20.3 Physical Interface 20.4 Software Break Points 20.5 Limitations of debugWIRE 20.6 debugWIRE Related Register in I/O Memory 20.6.1 debugWire Data Register - DWDR 21. Boot Loader Support - Read-While-Write Self-Programming 21.1 Boot Loader Features 21.2 Application and Boot Loader Flash Sections 21.2.1 Application Section 21.2.2 BLS - Boot Loader Section 21.3 Read-While-Write and No Read-While-Write Flash Sections 21.3.1 RWW - Read-While-Write Section 21.3.2 NRWW - No Read-While-Write Section 21.4 Boot Loader Lock Bits 21.5 Entering the Boot Loader Program 21.5.1 Store Program Memory Control and Status Register - SPMCSR 21.6 Addressing the Flash During Self-Programming 21.7 Self-Programming the Flash 21.7.1 Performing Page Erase by SPM 21.7.2 Filling the Temporary Buffer (Page Loading) 21.7.3 Performing a Page Write 21.7.4 Using the SPM Interrupt 21.7.5 Consideration While Updating BLS 21.7.6 Prevent Reading the RWW Section During Self-Programming 21.7.7 Setting the Boot Loader Lock Bits by SPM 21.7.8 EEPROM Write Prevents Writing to SPMCSR 21.7.9 Reading the Fuse and Lock Bits from Software 21.7.10 Preventing Flash Corruption 21.7.11 Programming Time for Flash when Using SPM 21.7.12 Simple Assembly Code Example for a Boot Loader 21.7.13 Boot Loader Parameters 22. Memory Programming 22.1 Program And Data Memory Lock Bits 22.2 Fuse Bits 22.3 PSC Output Behaviour During Reset 22.3.1 Latching of Fuses 22.4 Signature Bytes 22.5 Calibration Byte 22.6 Parallel Programming Parameters, Pin Mapping, and Commands 22.6.1 Signal Names 22.7 Serial Programming Pin Mapping 22.8 Parallel Programming 22.8.1 Enter Programming Mode 22.8.2 Considerations for Efficient Programming 22.8.3 Chip Erase 22.8.4 Programming the Flash 22.8.5 Programming the EEPROM 22.8.6 Reading the Flash 22.8.7 Reading the EEPROM 22.8.8 Programming the Fuse Low Bits 22.8.9 Programming the Fuse High Bits 22.8.10 Programming the Extended Fuse Bits 22.8.11 Programming the Lock Bits 22.8.12 Reading the Fuse and Lock Bits 22.8.13 Reading the Signature Bytes 22.8.14 Reading the Calibration Byte 22.8.15 Parallel Programming Characteristics 22.9 Serial Downloading 22.9.1 Serial Programming Algorithm 22.9.2 Data Polling Flash 22.9.3 Data Polling EEPROM 22.9.4 SPI Serial Programming Characteristics 23. Electrical Characteristics(1) 23.1 Absolute Maximum Ratings* 23.2 DC Characteristics 23.3 External Clock Drive Characteristics 23.3.1 Calibrated Internal RC Oscillator Accuracy 23.3.2 External Clock Drive Waveforms 23.3.3 External Clock Drive 23.4 Maximum Speed vs. VCC 23.5 PLL Characteristics 23.6 SPI Timing Characteristics 23.7 ADC Characteristics 23.8 Parallel Programming Characteristics 24. AT90PWM1 Typical Characteristics 24.1 Active Supply Current 24.2 Idle Supply Current 24.2.1 Using the Power Reduction Register 24.2.1.1 Example 1 24.2.1.2 Example 2 24.2.1.3 Example 3 24.2.2 Power consumption estimation with clock prescaling 24.2.2.1 Example 1 24.2.2.2 Example 2 24.3 Power-Down Supply Current 24.4 Pin Pull-up 24.5 Pin Driver Strength 24.6 Pin Thresholds and Hysteresis 24.7 BOD Thresholds and Analog Comparator Offset 24.8 Analog Reference 24.9 Internal Oscillator Speed 24.10 Current Consumption of Peripheral Units 24.11 Current Consumption in Reset and Reset Pulse width 25. Register Summary 26. Instruction Set Summary 27. Ordering Information 28. Package Information 28.1 SO24 28.2 QFN32 29. Errata 30. Datasheet Revision History for AT90PWM1 30.1 Changes from 4378A to 4378B 30.2 Changes from 4378B to 4378C Table of Contents