Datasheet AT90PWM81, AT90PWM161 - Complete (Atmel)

Features
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High performance, low power Atmel®AVR® 8-bit Microcontroller
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Advanced RISC architecture – 131 powerful instructions - most single clock cycle execution – 32 × 8 general purpose working registers – Fully static operation – Up to 1 MIPS throughput per MHz – On-chip 2-cycle multiplier
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Data and non-volatile program memory – 8/16Kbytes of in-system programmable program memory flash 8-bit Atmel • Endurance: 10,000 write/erase cycles Microcontroller • Lock bits protection • Optional 2/4Kbytes boot code section with independent lock bits with 8/16K • In-system programming by on-chip boot program • True read-while-write operation Bytes In-System – 512 Bytes of in-system programmable EEPROM • Four bytes page size Programmable – 256/1024 Bytes Internal SRAM
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On-chip debug support (debugWIRE) Flash
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Peripheral features – One 12-bit high speed PSC (Power Stage Controllers with extended PSC2 features) • Non overlapping inverted PWM output pins with flexible dead-time AT90PWM81 • Variable PWM duty cycle and frequency • Synchronous update of all PWM registers AT90PWM161 • Enhanced resolution mode (16 bits) • Additional register for ADC synchronization • Input capture • Four output pins and output matrix – One 12-bit high speed PSC (Power Stage Controller) • Auto-stop function for event driven PFC implementation • Non overlapping inverted PWM output pins with flexible dead-time • Variable PWM duty cycle and frequency • Synchronous update of all PWM registers • Enhanced resolution mode (16 bits) • Input capture – One 16-bit simple general purpose timer/counter – 10-bit ADC • Up to 11 single ended channels and one fully differential ADC channel pair • Programmable gain (5×, 10×, 20×, 40× on differential channel) • Internal reference voltage – One 10-bit DAC – Three analog comparators with • Resistor-array to adjust comparison voltage • DAC to adjust comparison voltage – One SPI – Three external interrupts – Programmable watchdog timer with separate on-chip oscillator
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Special microcontroller features – Low power idle, noise reduction, and power down modes
7734Q–AVR–02/12 Document Outline Features 1. Products Configuration 2. Pin Configurations 2.1 Pin Descriptions 2.1.1 VCC 2.1.2 GND 2.1.3 Port B (PB7..PB0) 2.1.4 Port D (PD7..PD0) 2.1.5 Port E (P32..0) RESET/XTAL1/XTAL2/AREF 2.1.6 AVCC 3. AVR CPU Core 3.1 Introduction 3.2 Architectural Overview 3.3 ALU – Arithmetic Logic Unit 3.4 Status Register 3.5 General Purpose Register File 3.5.1 The X-register, Y-register, and Z-register 3.6 Stack Pointer 3.7 Instruction Execution Timing 3.8 Reset and Interrupt Handling 3.8.1 Interrupt Behavior 3.8.2 Interrupt Response Time 4. Memories 4.1 In-System Reprogrammable Flash Program Memory 4.2 SRAM Data Memory 4.2.1 SRAM Data Access Times 4.3 EEPROM Data Memory 4.3.1 EEPROM Read/Write Access 4.3.2 EEARH and EEARL - EEPROM Address Registers 4.3.3 EEDR - EEPROM Data Register 4.3.4 EECR - EEPROM Control Register 4.3.5 Program multiple bytes in one Atomic operation 4.4 Fuse Bits 4.4.1 Code examples 4.4.2 Preventing EEPROM Corruption 4.5 I/O Memory 4.6 General Purpose I/O Registers 4.6.1 GPIOR0 - General Purpose I/O Register 0 4.6.2 GPIOR1 - General Purpose I/O Register 1 4.6.3 GPIOR2 - General Purpose I/O Register 2 5. System Clock and Clock Options 5.1 Clock Systems and their Distribution 5.1.1 clkCPU - CPU Clock 5.1.2 clkI/O - I/O Clock 5.1.3 clkFLASH - Flash Clock 5.1.4 clkPLL - PLL Clock 5.1.5 clkADC - ADC Clock 5.2 Clock Sources 5.2.1 Default Clock Source 5.2.2 Calibrated Internal RC Oscillator 5.2.2.1 RC Oscillator calibration at Factory 5.2.3 128KHz Internal Oscillator 5.2.4 Crystal Oscillator 5.2.5 External Clock 5.2.6 PLL 5.2.7 Clock Output Buffer 5.3 Dynamic Clock Switch 5.3.1 Features 5.3.2 Fuses substitution 5.3.3 Clock Source Selection 5.3.4 Enable/Disable Clock Source 5.3.5 Clock Availability 5.3.6 Clock Switching 1. Calibrated internal RC oscillator 8.0MHz/1.0MHz, 2. Internal watchdog oscillator 128kHz, 3. External clock, 4. External Crystal/Ceramic Resonator, 5. PLL output divided by four. 5.4 System Clock Prescaler 5.4.1 Features 5.4.2 Switching Time 5.5 Register Description 5.5.1 OSCCAL – Oscillator Calibration Register 5.5.2 CLKPR – Clock Prescaler Register 5.5.3 PLLCSR - PLL Control and Status Register 5.5.4 MCUCR - MCU Control Register 5.5.5 CLKCSR – Clock Control & Status Register 5.5.6 CLKSELR - Clock Selection Register 6. Power Management and Sleep Modes 6.1 Sleep Modes 6.2 Idle Mode 6.3 ADC Noise Reduction Mode 6.4 Power-down Mode 6.5 Standby Mode 6.6 Power Reduction Register 6.7 Minimizing Power Consumption 6.7.1 Analog to Digital Converter 6.7.2 Analog Comparator 6.7.3 Brown-out Detector 6.7.4 Internal Voltage Reference 6.7.5 Watchdog Timer 6.7.6 Port Pins 6.7.7 On-chip Debug System 6.8 Register description 6.8.1 SMCR - Sleep Mode Control Register 6.8.2 PRR - Power Reduction Register 7. System Control and Reset 7.1 System Control overview 7.1.1 Resetting the AVR 7.1.2 Reset Sources 7.1.3 Power-on Reset 7.1.4 External Reset 7.1.5 Brown-out Detection 7.1.6 Watchdog Reset 7.2 System Control registers 7.2.1 MCUSR - MCU Status Register 7.2.2 MCUCR - MCU Control Register 7.3 Internal Voltage Reference 7.3.1 Bandgap and Internal Voltage Reference Enable Signals and Start-up Time 7.3.2 Voltage Reference Characteristics 7.4 Watchdog Timer 7.4.1 WDTCSR - Watchdog Timer Control Register 8. Interrupts 8.1 Interrupt Vectors in AT90PWM81/161 8.1.1 Moving Interrupts Between Application and Boot Space 8.1.2 MCUCR - MCU Control Register 9. I/O-Ports 9.1 Introduction 9.2 Ports as General Digital I/O 9.2.1 Configuring the Pin 9.2.2 Toggling the Pin 9.2.3 Switching Between Input and Output 9.2.4 Reading the Pin Value 9.2.5 Digital Input Enable and Sleep Modes 9.3 Alternate Port Functions 9.3.1 MCUCR - MCU Control Register 9.3.2 Alternate Functions of Port B 9.3.3 Alternate Functions of Port D 9.3.4 Alternate Functions of Port E 9.4 Register Description for I/O-Ports 9.4.1 PORTB - Port B Data Register 9.4.2 DDRB - Port B Data Direction Register 9.4.3 PINB - Port B Input Pins Address 9.4.4 PORTD - Port D Data Register 9.4.5 DDRD - Port D Data Direction RegisterS 9.4.6 PIND - Port D Input Pins Address 9.4.7 PORTE - Port E Data Register 9.4.8 DDRE - Port E Data Direction Register 9.4.9 PINE - Port E Input Pins Address 10. External Interrupts 10.0.1 EICRA - External Interrupt Control Register A 10.0.2 EIMSK - External Interrupt Mask Register 10.0.3 EIFR - External Interrupt Flag Register 11. Reduced 16-bit Timer/Counter1 11.1 Overview 11.1.1 Registers 11.1.2 Definitions 11.2 Accessing 16-bit Registers 11.2.1 Reusing the Temporary High Byte Register 11.3 Timer/Counter Clock Sources 11.3.1 External Clock Source 11.4 Counter Unit 11.5 Input Capture Unit 11.5.1 Input Capture Trigger Source 11.5.2 Noise Canceler 11.5.3 Using the Input Capture Unit 11.6 Modes of Operation 11.6.1 Normal Mode 11.6.2 Clear Timer on Compare Match (CTC) Mode 11.7 Timer/Counter Timing Diagrams 11.8 16-bit Timer/Counter Register Description 11.8.1 TCCR1B - Timer/Counter1 Control Register B 11.8.2 TCNT1H and TCNT1L - Timer/Counter1 11.8.3 ICR1H and ICR1L - Input Capture Register 1 11.8.4 TIMSK1 - Timer/Counter1 Interrupt Mask Register 11.8.5 TIFR1 - Timer/Counter1 Interrupt Flag Register 12. Power Stage Controller – (PSCn) 12.1 Features 12.2 Overview 12.3 PSC Description 12.3.1 PSC2 Distinctive Feature 12.3.2 Output Polarity 12.4 Signal Description 12.4.1 Input Description 12.4.2 Output Description 12.5 Functional Description 12.5.1 Waveform Cycles 12.5.2 Running Mode Description 12.5.2.1 Four Ramp Mode 12.5.2.2 Two Ramp Mode 12.5.2.3 One Ramp Mode 12.5.2.4 Center Aligned Mode 12.5.3 Fifty Percent Waveform Configuration 12.6 Update of Values 12.6.1 Value Update Synchronization 12.7 Enhanced Resolution 12.7.1 Frequency distribution 12.7.2 Modes of Operation 12.7.2.1 Normal Mode 12.7.2.2 Enhanced Mode 12.8 PSC Inputs 12.8.1 PSC Retrigger Behavior versus PSC running modes 12.8.2 Retrigger PSCOUTn0 On External Event 12.8.3 Retrigger PSCOUTn1 On External Event 12.8.3.1 Burst Generation 12.8.4 PSC Input Configuration 12.8.4.1 Filter Enable 12.8.4.2 Signal Polarity 12.8.4.3 Input Mode Operation 12.9 PSC Input Mode 1: Stop signal, Jump to Opposite Dead-Time and Wait 12.10 PSC Input Mode 2: Stop signal, Execute Opposite Pulse and Wait 12.11 PSC Input Mode 3: Stop signal, Execute Opposite Pulse while Fault active 12.12 PSC Input Mode 4: Deactivate outputs without changing timing 12.13 PSC Input Mode 5: Stop signal and Insert Dead-Time 12.14 PSC Input Mode 6: Stop signal, Jump to Opposite Dead-Time and Wait 12.15 PSC Input Mode 7: Halt PSC and Wait for Software Action 12.16 PSC Input Mode 8: Edge Retrigger PSC 12.17 PSC Input Mode 9: Fixed Frequency Edge Retrigger PSC 12.18 PSC Input Mode 14: Fixed Frequency Edge Retrigger PSC and Deactivate Output 12.18.1 Available Input Mode according to Running Mode 12.18.2 Event Capture 12.18.3 Using the Input Capture Unit 12.19 PSC2 Outputs 12.19.1 Output Matrix 12.19.2 PSCOUT22 & PSCOUT23 Selectors 12.20 Analog Synchronization 12.21 Interrupt Handling 12.22 PSC Synchronization 12.22.1 Fault events in Autorun mode 12.23 PSC Clock Sources 12.24 Interrupts 12.24.1 List of Interrupt Vector 12.25 PSC Register Definition 12.25.1 PSOC2 - PSC 2 Synchro and Output Configuration 12.25.2 OCRnSAH and OCRnSAL - Output Compare SA Register 12.25.3 OCRnRAH and OCRnRAL - Output Compare RA Register 12.25.4 OCRnSBH and OCRnSBL - Output Compare SB Register 12.25.5 OCRnRBH and OCRnRBL - Output Compare RB Register 12.25.6 PCNF2 - PSC 2 Configuration Register 12.25.7 PCNFE2 - PSC 2 Extended Configuration Register 12.25.8 PASDLYn - Analog Synchronization Delay Register 12.25.9 PCTL2 - PSC 2 Control Register 12.25.10 PFRCnA - PSC n Input A Control Register 12.25.11 PFRCnB - PSC n Input B Control Register 12.25.12 PICR2H and PICR2L - PSC 2 Input Capture Register 12.26 PSC2 Specific Register 12.26.1 POM2 - PSC 2 Output Matrix 12.26.2 PIM2 - PSC2 Interrupt Mask Register 12.26.3 PIFR2 - PSC2 Interrupt Flag Register 12.26.4 PSC Output Behavior During Reset 12.26.5 PSC Input Behavior During Reset 13. Reduced Power Stage Controller – (PSCR) 13.1 Features 13.2 Overview 13.3 PSCR Description 13.3.1 Output Polarity 13.4 Signal Description 13.4.1 Input Description 13.4.2 Output Description 13.5 Functional Description 13.5.1 Waveform Cycles 13.5.2 Running Mode Description 13.5.2.1 Four Ramp Mode 13.5.2.2 Two Ramp Mode 13.5.2.3 One Ramp Mode 13.5.3 Fifty Percent Waveform Configuration 13.6 Update of Values 13.6.1 Value Update Synchronization 13.7 Enhanced resolution 13.8 PSCR Inputs 13.8.1 PSCR Retrigger Behavior versus PSCR running modes 13.8.2 Retrigger PSCOUTr0 On External Event 13.8.3 Retrigger PSCOUTr1 On External Event 13.8.3.1 Burst Generation 13.8.4 PSCR Input Configuration 13.8.4.1 Filter Enable 13.8.4.2 Signal Polarity 13.8.4.3 Input Mode Operation 13.9 PSCR Input Mode 1: Stop signal, Jump to Opposite Dead-Time and Wait 13.10 PSCR Input Mode 2: Stop signal, Execute Opposite Dead-Time and Wait 13.11 PSCR Input Mode 3: Stop signal, Execute Opposite while Fault active 13.12 PSCR Input Mode 4: Deactivate outputs without changing timing 13.13 PSCR Input Mode 5: Stop signal and Insert Dead-Time 13.14 PSCR Input Mode 6: Stop signal, Jump to Opposite Dead-Time and Wait 13.15 PSCR Input Mode 7: Halt PSCR and Wait for Software Action 13.16 PSCR Input Mode 8: Edge Retrigger PSC 13.17 PSCR Input Mode 9: Fixed Frequency Edge Retrigger PSC 13.18 PSCR Input Mode 14: Fixed Frequency Edge Retrigger PSCR and Deactivate Output 13.18.1 Available Input Mode according to Running Mode 13.18.2 Event Capture 13.18.3 Using the Input Capture Unit 13.19 Analog Synchronization 13.20 Interrupt Handling 13.21 PSC Clock Sources 13.22 Interrupts 13.22.1 List of Interrupt Vector 13.23 PSCR Register Definition 13.23.1 PSOC0 - PSCR Synchro and Output Configuration 13.23.2 OCR0SAH and OCR0SAL - Output Compare SA Register 13.23.3 OCR0RAH and OCR0RAL - Output Compare RA Register 13.23.4 OCR0SBH and OCR0SBL - Output Compare SB Register 13.23.5 OCR0RBH and OCR0RBL - Output Compare RB Register 13.23.6 PCNF0 - PSCR Configuration Register 13.23.7 PCTL0 - PSCR Control Register 13.23.8 PFRC0A - PSCR Input A Control Register 13.23.9 PFRC0B - PSCR Input B Control Register 13.23.10 PICR0H and PICR0L - PSCR Input Capture Register 13.23.11 PIM0 - PSCR Interrupt Mask Register 13.23.12 PIFR0 - PSCR Interrupt Flag Register 14. Serial Peripheral Interface – SPI: 14.1 Features 14.2 Overview 14.3 SS Pin Functionality 14.3.1 Slave Mode 14.3.2 Master Mode 14.4 Data Modes 14.5 SPI registers 14.5.1 SPCR - SPI Control Register 14.5.2 SPSR - SPI Status Register 14.5.3 SPDR - SPI Data Register 15. Voltage Reference and Temperature Sensor 15.1 Features 15.2 On Chip voltage Reference and Temperature sensor overview 15.3 Register Description 15.3.1 BGCCR – Bandgap Calibration Current Register 15.3.2 BGCRR – Bandgap Calibration Resistor Register 15.4 Temperature Measurement 15.4.1 Manufacturing Calibration 16. Analog Comparator 16.1 Features 16.2 Overview 16.3 Shared pins between Analog Comparator and ADC 16.4 Analog Comparator Register Description 16.4.1 AC1CON - Analog Comparator 1 Control Register 16.4.2 AC2CON - Analog Comparator 2 Control Register 16.4.3 AC3CON - Analog Comparator 3 Control Register 16.4.4 ACnECON - Analog Comparator n Extended Control Register 16.4.5 ACSR - Analog Comparator Status Register 16.4.6 DIDR0 - Digital Input Disable Register 0 16.4.7 DIDR1 - Digital Input Disable Register 1 17. Analog to Digital Converter - ADC 17.1 Features 17.2 Operation 17.3 Starting a Conversion 17.4 Prescaling and Conversion Timing 17.5 Changing Channel or Reference Selection 17.5.1 ADC Input Channels 17.5.2 ADC Voltage Reference 17.6 ADC Noise Canceler 17.6.1 Analog Input Circuitry 17.6.2 Analog Noise Canceling Techniques 17.6.3 Offset Compensation Schemes 17.6.4 ADC Accuracy Definitions 17.7 ADC Conversion Result 17.8 ADC Register Description 17.8.1 ADMUX - ADC Multiplexer Register 17.8.2 ADCSRA - ADC Control and Status Register A 17.8.3 ADCSRB - ADC Control and Status Register B 17.8.4 ADCH and ADCL - ADC Result Data Registers 17.8.4.1 ADLAR = 0 17.8.4.2 ADLAR = 1 17.8.5 DIDR0 - Digital Input Disable Register 0 17.8.6 DIDR1 - Digital Input Disable Register 1 17.9 Amplifier 17.10 Amplifier Control Registers 17.10.1 AMP0CSR - Amplifier 0 Control and Status register 18. Digital to Analog Converter - DAC 18.1 Features 18.2 Operation 18.3 Starting a Conversion 18.3.1 DAC Voltage Reference 18.4 DAC Register Description 18.4.1 DACON - Digital to Analog Conversion Control Register 18.4.2 DACH and DACL - Digital to Analog Converter input Register 18.4.2.1 DALA = 0 18.4.2.2 DALA = 1 19. debugWIRE On-chip Debug System 19.1 Features 19.2 Overview 19.3 Physical Interface 19.4 Software Break Points 19.5 Limitations of debugWIRE 19.6 debugWIRE Related Register in I/O Memory 19.6.1 DWDR - debugWire Data Register 20. Boot Loader Support – Read-While-Write Self-Programming 20.1 Boot Loader Features 20.2 Application and Boot Loader Flash Sections 20.2.1 Application Section 20.2.2 BLS – Boot Loader Section 20.3 Read-While-Write and No Read-While-Write Flash Sections 20.3.1 RWW – Read-While-Write Section 20.3.2 NRWW – No Read-While-Write Section 20.4 Boot Loader Lock Bits 20.5 Entering the Boot Loader Program 20.5.1 SPMCSR - Store Program Memory Control and Status Register 20.6 Addressing the Flash During Self-Programming 20.7 Self-Programming the Flash 20.7.1 Performing Page Erase by SPM 20.7.2 Filling the Temporary Buffer (Page Loading) 20.7.3 Performing a Page Write 20.7.4 Using the SPM Interrupt 20.7.5 Consideration While Updating BLS 20.7.6 Prevent Reading the RWW Section During Self-Programming 20.7.7 Setting the Boot Loader Lock Bits by SPM 20.7.8 EEPROM Write Prevents Writing to SPMCSR 20.7.9 Reading the Fuse and Lock Bits from Software 20.7.10 Reading the Signature Row from Software 20.7.11 Preventing Flash Corruption 20.7.12 Programming Time for Flash when Using SPM 20.7.13 Simple Assembly Code Example for a Boot Loader 20.7.14 Boot Loader Parameters 21. Memory Programming 21.1 Program And Data Memory Lock Bits 21.2 Fuse Bits 21.2.1 PSC Output Behavior During Reset 21.2.2 PSC Input Behavior During Reset 21.2.3 Latching of Fuses 21.3 Signature Bytes 21.3.1 Signature Bytes 21.4 Calibration Byte 21.5 Parallel Programming Parameters, Pin Mapping, and Commands 21.5.1 Signal Names 21.6 Serial Programming Pin Mapping 21.7 Parallel Programming 21.7.1 Enter Programming Mode 21.7.2 Considerations for Efficient Programming 21.7.3 Chip Erase 21.7.4 Programming the Flash 21.7.5 Programming the EEPROM 21.7.6 Reading the Flash 21.7.7 Reading the EEPROM 21.7.8 Programming the Fuse Low Bits 21.7.9 Programming the Fuse High Bits 21.7.10 Programming the Extended Fuse Bits 21.7.11 Programming the Lock Bits 21.7.12 Reading the Fuse and Lock Bits 21.7.13 Reading the Signature Bytes 21.7.14 Reading the Calibration Byte 21.8 Serial Downloading 21.8.1 Serial Programming Algorithm 21.8.2 Data Polling Flash 21.8.3 Data Polling EEPROM 21.8.4 SPI Serial Programming Characteristics 22. Electrical Characteristics (1) 22.1 Absolute Maximum Ratings* 22.2 DC Characteristics 22.3 Clock Drive Characteristics 22.3.1 Calibrated Internal RC Oscillator Accuracy 22.3.2 Watchdog Oscillator Accuracy 22.3.3 External Clock Drive Waveforms 22.3.4 External Clock Drive 22.4 Maximum Speed vs. VCC 22.5 PLL Characteristics 22.6 SPI Timing Characteristics 22.7 ADC Characteristics 22.8 DAC Characteristics 22.9 Parallel Programming Characteristics 23. AT90PWM81/161 Typical Characteristics 23.1 Active Supply Current 23.2 Idle Supply Current 23.3 Power-Down Supply Current 23.4 Pin Pull-up 23.5 Pin output high voltage 23.6 Pin output low voltage 23.7 Pin Thresholds 23.8 BOD Thresholds 23.9 Analog Reference 23.10 Internal Oscillator Speed 23.11 Current Consumption in Reset 24. Register Summary 25. Instruction Set Summary 26. Ordering Information 26.1 SO20 26.2 QFN32 27. Errata 27.1 Errata AT90PWM81 revA 27.2 Errata AT90PWM81 revB 27.3 Errata AT90PWM81 revC 27.4 Errata AT90PWM81 revD 27.5 Errata AT90PWM81 revE 27.6 Errata AT90PWM161 revA 27.7 Errata AT90PWM161 revB 28. Datasheet Revision History for AT90PWM81/161 28.1 Rev. 7734A 28.2 Rev. 7734B 28.3 Rev. 7734C 28.4 Rev. 7734D 28.5 Rev. 7734E 28.6 Rev. 7734F 28.7 Rev. 7734G 28.8 Rev. 7734H 28.9 Rev. 7734I 28.10 Rev. 7734J 28.11 Rev. 7734K 28.12 Rev. 7734L 28.13 Rev. 7734M 28.14 Rev. 7734N 28.15 Rev. 7734O 28.16 Rev. 7734P 28.17 Rev. 7734Q Table Of Contents