Datasheet AT90S8515 (Atmel) - 8
| 制造商 | Atmel |
| 描述 | 8-bit AVR Microcontroller with 8K Bytes In-System Programmable Flash |
| 页数 / 页 | 112 / 8 — Figure 4. The AT90S8515 AVR RISC Architecture Data Bus 8-bit 4K x 16. … |
| 文件格式/大小 | PDF / 2.7 Mb |
| 文件语言 | 英语 |
Figure 4. The AT90S8515 AVR RISC Architecture Data Bus 8-bit 4K x 16. Program. Memory Program. Counter Status. and Test 32 x 8
该数据表的模型线
- AT90S8515-4AC AT90S8515-4AI AT90S8515-4JC AT90S8515-4JI AT90S8515-4PC AT90S8515-4PI AT90S8515-8AC AT90S8515-8AI AT90S8515-8JC AT90S8515-8JI AT90S8515-8PC AT90S8515-8PI AT90S8515A-4AC AT90S8515A-4AI AT90S8515A-4JC AT90S8515A-4JI AT90S8515A-4PC AT90S8515A-4PI AT90S8515A-8AC AT90S8515A-8AI AT90S8515A-8JC AT90S8515A-8JI AT90S8515A-8PC AT90S8515A-8PI
文件文字版本
Figure 4. The AT90S8515 AVR RISC Architecture Data Bus 8-bit 4K x 16
Program
Memory Program
Counter Status
and Test 32 x 8
General
Purpose
Registers Control Lines Indirect Addressing Instruction
Decoder Direct Addressing Instruction
Register Control
Registers
Interrupt
Unit
SPI
Unit
Serial
UART ALU
8-bit
Timer/Counter 512 x 8
Data
SRAM 512 x 8
EEPROM 16-bit
Timer/Counter
with PWM
Watchdog
Timer
Analog
Comparator
32
I/O Lines A flexible interrupt module has its control registers in the I/O space with an additional
global interrupt enable bit in the status register. All the different interrupts have a separate interrupt vector in the interrupt vector table at the beginning of the program
memory. The different interrupts have priority in accordance with their interrupt vector
position. The lower the interrupt vector address, the higher the priority. 8 AT90S8515
0841G–09/01
Program
Memory Program
Counter Status
and Test 32 x 8
General
Purpose
Registers Control Lines Indirect Addressing Instruction
Decoder Direct Addressing Instruction
Register Control
Registers
Interrupt
Unit
SPI
Unit
Serial
UART ALU
8-bit
Timer/Counter 512 x 8
Data
SRAM 512 x 8
EEPROM 16-bit
Timer/Counter
with PWM
Watchdog
Timer
Analog
Comparator
32
I/O Lines A flexible interrupt module has its control registers in the I/O space with an additional
global interrupt enable bit in the status register. All the different interrupts have a separate interrupt vector in the interrupt vector table at the beginning of the program
memory. The different interrupts have priority in accordance with their interrupt vector
position. The lower the interrupt vector address, the higher the priority. 8 AT90S8515
0841G–09/01