Datasheet AT90S4433, AT90LS4433 (Atmel) - 10

General Purpose
Figure 7 shows the structure of the 32 general purpose working registers in the CPU.
Register File Figure 7.
AVR CPU General Purpose Working Registers 7 0 Addr. R0 $00 R1 $01 R2 $02 … R13 $0D General R14 $0E Purpose R15 $0F Working R16 $10 Registers R17 $11 … R26 $1A X-register Low Byte R27 $1B X-register High Byte R28 $1C Y-register Low Byte R29 $1D Y-register High Byte R30 $1E Z-register Low Byte R31 $1F Z-register High Byte All the register operating instructions in the instruction set have direct and single cycle access to all registers. The only exceptions are the five constant arithmetic and logic instructions SBCI, SUBI, CPI, ANDI, and ORI between a constant and a register, and the LDI instruction for load immediate constant data. These instructions apply to the second half of the registers in the Register File (R16..R31). The general SBC, SUB, CP, AND, and OR, and all other operations between two registers or on a single register apply to the entire Register File. As shown in Figure 7, each register is also assigned a data memory address, mapping them directly into the first 32 locations of the user Data Space. Although not being phys- ically implemented as SRAM locations, this memory organization provides great flexibility in access of the registers, as the X-, Y- ,and Z-registers can be set to index any register in the file.
X-register, Y-register and Z-
The registers R26..R31 have some added functions to their general purpose usage.
register
These registers are address pointers for indirect addressing of the Data Space. The three indirect address registers X, Y, and Z are defined as:
Figure 8.
X-, Y-, and Z-registers 15 0 X - register 7 0 7 0 R27 ($1B) R26 ($1A) 15 0 Y - register 7 0 7 0 R29 ($1D) R28 ($1C) 15 0 Z - register 7 0 7 0 R31 ($1F) R30 ($1E)
10 AT90S/LS4433
1042H–AVR–04/03 Document Outline Features Pin Configurations Description Block Diagram Pin Descriptions VCC GND Port B (PB5..PB0) Port C (PC5..PC0) Port D (PD7..PD0) RESET XTAL1 XTAL2 AVCC AREF AGND Clock Options Crystal Oscillator External Clock Architectural Overview General Purpose Register File X-register, Y-register and Z- register ALU – Arithmetic Logic Unit In-System Programmable Flash Program Memory SRAM Data Memory Program and Data Addressing Modes Register Direct, Single Register Rd Register Direct, Two Registers Rd and Rr I/O Direct Data Direct Data Indirect with Displacement Data Indirect Data Indirect with Pre- decrement Data Indirect with Post- increment Constant Addressing Using the LPM Instruction Indirect Program Addressing, IJMP and ICALL Relative Program Addressing, RJMP and RCALL EEPROM Data Memory Memory Access Times and Instruction Execution Timing I/O Memory Status Register – SREG Stack Pointer – SP Reset and Interrupt Handling Reset Sources Power-on Reset External Reset Brown-out Detection Watchdog Reset MCU Status Register – MCUSR Interrupt Handling General Interrupt Mask Register – GIMSK General Interrupt Flag Register – GIFR Timer/Counter Interrupt Mask Register – TIMSK Timer/Counter Interrupt Flag Register – TIFR External Interrupts Interrupt Response Time MCU Control Register – MCUCR Sleep Modes Idle Mode Power-down Mode Timer/Counters Timer/Counter Prescaler 8-bit Timer/Counter0 Timer/Counter0 Control Register – TCCR0 Timer Counter0 – TCNT0 16-bit Timer/Counter1 Timer/Counter1 Control Register A – TCCR1A Timer/Counter1 Control Register B – TCCR1B Timer/Counter1 – TCNT1H and TCNT1L Timer/Counter1 Output Compare Register – OCR1H and OCR1L Timer/Counter1 Input Capture Register – ICR1H and ICR1L Timer/Counter1 in PWM Mode Watchdog Timer Watchdog Timer Control Register – WDTCR EEPROM Read/Write Access EEPROM Address Register – EEAR EEPROM Data Register – EEDR EEPROM Control Register – EECR Prevent EEPROM Corruption Serial Peripheral Interface – SPI SS Pin Functionality Data Modes SPI Control Register – SPCR SPI Status Register – SPSR SPI Data Register – SPDR UART Data Transmission Data Reception Multi-processor Communication Mode UART Control UART I/O Data Register – UDR UART Control and Status Register A – UCSRA UART Control and Status Register B – UCSRB Baud Rate Generator UART Baud Rate Register – UBRR Analog Comparator Analog Comparator Control and Status Register – ACSR Analog-to-Digital Converter Features Operation Prescaling ADC Noise Canceler Function ADC Multiplexer Select Register – ADMUX ADC Control and Status Register – ADCSR ADC Data Register – ADCL AND ADCH Scanning Multiple Channels ADC Noise Canceling Techniques ADC Characteristics TA = -40°C to 85°C I/O Ports Port B Port B Data Register – PORTB Port B Data Direction Register – DDRB Port B Input Pins Address – PINB Port B as General Digital I/O Alternate Functions of Port B Port C Port C Data Register – PORTC Port C Data Direction Register – DDRC Port C Input Pins Address – PINC Port C as General Digital I/O Port C Schematics Port D Port D Data Register – PORTD Port D Data Direction Register – DDRD Port D Input Pins Address – PIND Port D as General Digital I/O Alternate Functions of Port D Port D Schematics Memory Programming Program and Data Memory Lock Bits Fuse Bits Signature Bytes Programming the Flash and EEPROM Parallel Programming Signal Names Enter Programming Mode Chip Erase Programming the Flash Reading the Flash Programming the EEPROM Reading the EEPROM Programming the Fuse Bits Programming the Lock Bits Reading the Fuse and Lock Bits Reading the Signature Bytes Parallel Programming Characteristics Serial Downloading Serial Programming Algorithm Data Polling EEPROM Data Polling Flash Serial Programming Characteristics Electrical Characteristics Absolute Maximum Ratings* DC Characteristics External Clock Drive Waveforms Typical Characteristics Register Summary Instruction Set Summary Ordering Information Packaging Information 32A 28P3 Errata for AT90S/LS4433 Rev. Rev. C/D/E/F Data Sheet ChangeLog for AT90S/LS4433 Changes from Rev. 1042E-09/01 to Ref. 1042F-03/02 Changes from Rev. 1042F-03/02 to Ref. 1042G-09/02 Changes from Rev. 1042G-09/02 to Ref. 1042H-04/03 Table of Contents