Datasheet AT90S4414, AT90S8515 (Atmel) - 9

link to page 77 link to page 10
AT90S4414/8515 ALU - Arithmetic Logic Unit
The high-performance AVR ALU operates in direct connection with all the 32 general purpose working registers. Within a single clock cycle, ALU operations between registers in the register file are executed. The ALU operations are divided into three main categories - arithmetic, logical and bit-functions.
In-System Programmable Flash Program Memory
The AT90S4414/8515 contains 4K/8K bytes on-chip In-System Programmable Flash memory for program storage. Since all instructions are 16-or 32-bit words, the Flash is organized as 2K x 16/4K x 16. The Flash memory has an endurance of at least 1000 write/erase cycles. The AT90S4414/8515 Program Counter (PC) is 11/12 bits wide, thus addressing the 2048/4096 program memory addresses. See page 77 for a detailed description on Flash data downloading. See page 10 for the different program memory addressing modes.
SRAM Data Memory - Internal and External
The following figure shows how the AT90S4414/8515 SRAM Memory is organized:
Figure 8.
SRAM Organization Register File Data Address Space R0 $0000 R1 $0001 R2 $0002 … … R29 $001D R30 $001E R31 $001F I/O Registers $00 $0020 $01 $0021 $02 $0022 … … $3D $005D $3E $005E $3F $005F Internal SRAM $0060 $0061 … $015E/$025E $015F/$025F External SRAM $0160/$0260 $0161/$0261 … $FFFE $FFFF
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Document Outline Features Description Block Diagram Comparison Between AT90S4414 and AT90S8515 Pin Descriptions VCC GND Port A (PA7..PA0) Port B (PB7..PB0) Port C (PC7..PC0) Port D (PD7..PD0) RESET XTAL1 XTAL2 ICP OC1B ALE Crystal Oscillator Architectural Overview General Purpose Register File X-Register, Y-Register And Z-Register ALU - Arithmetic Logic Unit In-System Programmable Flash Program Memory SRAM Data Memory - Internal and External Program and Data Addressing Modes Register Direct, Single Register RD Register Direct, Two Registers Rd and Rr I/O Direct Data Direct Data Indirect with Displacement Data Indirect Data Indirect with Pre-decrement Data Indirect with Post-increment Constant Addressing Using the LPM Instruction Indirect Program Addressing, IJMP and ICALL Relative Program Addressing, RJMP and RCALL EEPROM Data Memory Memory Access Times and Instruction Execution Timing I/O Memory Status Register - SREG Stack Pointer - SP Reset and Interrupt Handling Reset Sources Power-on Reset External Reset Watchdog Reset Interrupt Handling General Interrupt Mask Register - GIMSK General Interrupt Flag Register - GIFR Timer/counter Interrupt Mask Register - TIMSK Timer/Counter Interrupt Flag Register - TIFR External Interrupts Interrupt Response Time MCU Control Register - MCUCR Sleep Modes Idle Mode Power Down Mode Timer/Counters Timer/Counter Prescaler 8-bit Timer/Counter0 Timer/Counter0 Control Register - TCCR0 Timer Counter 0 - TCNT0 16-bit Timer/Counter1 Timer/Counter1 Control Register A - TCCR1A Timer/Counter1 Control Register B - TCCR1B Timer/Counter1 - TCNT1H AND TCNT1L Timer/Counter1 Output Compare Register - OCR1AH AND OCR1AL Timer/Counter1 Output Compare Register - OCR1BH AND OCR1BL Timer/Counter1 Input Capture Register - ICR1H AND ICR1L Timer/Counter1 In PWM Mode Watchdog Timer Watchdog Timer Control Register - WDTCR EEPROM Read/Write Access EEPROM Address Register - EEARH and EEARL EEPROM Data Register - EEDR EEPROM Control Register - EECR Prevent EEPROM Corruption Serial Peripheral Interface - SPI SS Pin Functionality Data Modes SPI Control Register - SPCR SPI Status Register - SPSR SPI Data Register - SPDR UART Data Transmission Data Reception UART Control UART I/O Data Register - UDR UART Status Register - USR UART Control Register - UCR BAUD Rate Generator UART BAUD Rate Register - UBRR Analog Comparator Analog Comparator Control And Status Register - ACSR Interface to External SRAM I/O-Ports Port A Port A Data Register - PORTA Port A Data Direction Register - DDRA Port A Input Pins Address - PINA Port A as General Digital I/O Port A Schematics Port B Port B Data Register - PORTB Port B Data Direction Register - DDRB Port B Input Pins Address - PINB PortB as General Digital I/O Alternate Functions of PortB Port B Schematics Port C Port C Data Register - PORTC Port C Data Direction Register - DDRC Port C Input Pins Address - PINC PortC as General Digital I/O Port C Schematics Port D Port D Data Register - PORTD Port D Data Direction Register - DDRD Port D Input Pins Address - PIND PortD as General Digital I/O Alternate Functions Of Port D PortD Schematics Memory Programming Program and Data Memory Lock Bits Fuse Bits Signature Bytes Programming the Flash and EEPROM Parallel Programming Signal Names Enter Programming Mode Chip Erase Programming the Flash Reading the Flash Programming the EEPROM Reading the EEPROM Programming the Fuse Bits Programming the Lock Bits Reading the Fuse and Lock Bits Reading the Signature Bytes Parallel Programming Characteristics Serial Downloading Serial Programming Algorithm Data Polling EEPROM Data Polling Flash Serial Programming Characteristics Electrical Characteristics Absolute Maximum Ratings* DC Characteristics External Clock Drive Waveforms External Data Memory Timing Typical Characteristics Instruction Set Summary (Continued) Ordering Information