Datasheet AT90S2333, AT90LS2333, AT90S4433, AT90LS4433 - Preliminary (Atmel) - 5
| 制造商 | Atmel |
| 描述 | 8-bit AVR Microcontroller with 2K/4K bytes In-System Programmable Flash |
| 页数 / 页 | 13 / 5 — AT90S/LS2333 and AT90S/LS4433. Architectural Overview. Figure 2 |
| 文件格式/大小 | PDF / 320 Kb |
| 文件语言 | 英语 |
AT90S/LS2333 and AT90S/LS4433. Architectural Overview. Figure 2
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文件文字版本
link to page 5
AT90S/LS2333 and AT90S/LS4433 Architectural Overview
The fast-access register file concept contains 32 x 8-bit general purpose working registers with a single clock cycle access time. This means that during one single clock cycle, one Arithmetic Logic Unit (ALU) operation is executed. Two operands are output from the register file, the operation is executed, and the result is stored back in the register file - in one clock cycle. Six of the 32 registers can be used as three 16-bits indirect address register pointers for Data Space addressing - enabling efficient address calculations. One of the three address pointers is also used as the address pointer for the constant table look up function. These added function registers are the 16-bits X-register, Y-register and Z-register. The ALU supports arithmetic and logic functions between registers or between a constant and a register. Single register operations are also executed in the ALU. Figure 2 shows the AT90S2333/4433 AVR RISC microcontroller architecture. In addition to the register operation, the conventional memory addressing modes can be used on the register file as well. This is enabled by the fact that the register file is assigned the 32 lowermost Data Space addresses ($00 - $1F), allowing them to be accessed as though they were ordinary memory locations.
Figure 2.
The AT90S2333/4433 AVR RISC Architecture AVR AT90S2333/4433 Architecture Data Bus 8-bit Program Status Interrupt 1K/2K X 16 Counter and Control Unit Program Memory SPI 32 x 8 Unit Instruction General Register Purpose Registrers Serial UART Instruction Decoder 8-bit ALU Timer/Counter Control Lines 16-bit Timer/Counter Direct Addressing Indirect Addressing with PWM 128 x 8 Data Watchdog SRAM Timer Analog to Digital 128/256 x 8 Converter EEPROM 20 Analog I/O Lines Comparator
5
Document Outline Features Description Block Diagram Pin Descriptions VCC GND Port B (PB5..PB0) Port C (PC5..PC0) Port D (PD7..PD0) RESET XTAL1 XTAL2 AVCC AREF AGND Architectural Overview Register Summary (Continued) Instruction Set Summary (Continued) Ordering Information Pin Configurations
AT90S/LS2333 and AT90S/LS4433 Architectural Overview
The fast-access register file concept contains 32 x 8-bit general purpose working registers with a single clock cycle access time. This means that during one single clock cycle, one Arithmetic Logic Unit (ALU) operation is executed. Two operands are output from the register file, the operation is executed, and the result is stored back in the register file - in one clock cycle. Six of the 32 registers can be used as three 16-bits indirect address register pointers for Data Space addressing - enabling efficient address calculations. One of the three address pointers is also used as the address pointer for the constant table look up function. These added function registers are the 16-bits X-register, Y-register and Z-register. The ALU supports arithmetic and logic functions between registers or between a constant and a register. Single register operations are also executed in the ALU. Figure 2 shows the AT90S2333/4433 AVR RISC microcontroller architecture. In addition to the register operation, the conventional memory addressing modes can be used on the register file as well. This is enabled by the fact that the register file is assigned the 32 lowermost Data Space addresses ($00 - $1F), allowing them to be accessed as though they were ordinary memory locations.
Figure 2.
The AT90S2333/4433 AVR RISC Architecture AVR AT90S2333/4433 Architecture Data Bus 8-bit Program Status Interrupt 1K/2K X 16 Counter and Control Unit Program Memory SPI 32 x 8 Unit Instruction General Register Purpose Registrers Serial UART Instruction Decoder 8-bit ALU Timer/Counter Control Lines 16-bit Timer/Counter Direct Addressing Indirect Addressing with PWM 128 x 8 Data Watchdog SRAM Timer Analog to Digital 128/256 x 8 Converter EEPROM 20 Analog I/O Lines Comparator
5
Document Outline Features Description Block Diagram Pin Descriptions VCC GND Port B (PB5..PB0) Port C (PC5..PC0) Port D (PD7..PD0) RESET XTAL1 XTAL2 AVCC AREF AGND Architectural Overview Register Summary (Continued) Instruction Set Summary (Continued) Ordering Information Pin Configurations