Datasheet ATtiny22, ATtiny22L - Preliminary (Atmel) - 4

Figure 2.
External Clock Drive Configuration PB3
Architectural Overview
The fast-access register file concept contains 32 x 8-bit general purpose working registers with a single clock cycle access time. This means that during one single clock cycle, one arithmetic logic unit (ALU) operation is executed. Two operands are output from the register file, the operation is executed, and the result is stored back in the register file in one clock cycle. Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing enabling efficient address calculations. One of the three address pointers is also used as the address pointer for the constant table look up function. These added function registers are the 16-bit X-register, Y-register and Z-register.
Figure 3.
The ATtiny22/L AVR RISC Architecture AVR ATtiny22/L Architecture Data Bus 8-bit Program Status Control 1K x 16 Counter and Test Registers Program Flash Interrupt 32 x 8 Unit Instruction General Register Purpose Registers SPI Unit Instruction Decoder 8-bit Timer/Counter ALU Control Lines Watchdog Timer Direct Addressing Indirect Addressing I/O Lines 128 x 8 Data SRAM 128 x 8 EEPROM
4 ATtiny22/22L
Document Outline Features Description Block Diagram Pin Descriptions ATtiny22/L VCC GND Port B (PB4..PB0) RESET CLOCK Clock Options External Clock Architectural Overview General Purpose Register File X-Register, Y-Register, and Z-Register ALU - Arithmetic Logic Unit In-System Programmable Flash Program Memory EEPROM Data Memory SRAM Data Memory Program and Data Addressing Modes Register Direct, Single Register Rd Register Direct, Two Registers Rd and Rr I/O Direct Data Direct Data Indirect with Displacement Data Indirect Data Indirect With Pre-Decrement Data Indirect With Post-Increment Constant Addressing Using the LPM Instruction Indirect Program Addressing, IJMP and ICALL Relative Program Addressing, RJMP and RCALL Memory Access and Instruction Execution Timing I/O Memory Status Register - SREG Stack Pointer - SPL Reset and Interrupt Handling Reset Sources Power-On Reset External Reset Watchdog Reset MCU Status Register - MCUSR Interrupt Handling General Interrupt Mask Register - GIMSK General Interrupt Flag Register - GIFR Timer/Counter Interrupt Mask Register - TIMSK Timer/Counter Interrupt FLAG Register - TIFR External Interrupt Interrupt Response Time MCU Control Register - MCUCR Sleep Modes Idle Mode Power Down Mode Timer/Counter Timer/Counter Prescaler 8-Bit Timer/Counter0 Timer/Counter0 Control Register - TCCR0 Timer Counter 0 - TCNT0 Watchdog Timer Watchdog Timer Control Register - WDTCR EEPROM Read/Write Access EEPROM Address Register - EEAR EEPROM Data Register - EEDR EEPROM Control Register - EECR Prevent EEPROM Corruption I/O Port B Port B Data Register - PORTB Port B Data Direction Register - DDRB Port B Input Pins Address - PINB General Digital I/O Alternate Functions of Port B CLOCK - Port B, Bit 3 SCK/T0 - Port B, Bit 2 MISO - Port B, Bit 1 MOSI - Port B, Bit 0 Memory Programming Program and Data Memory Lock Bits Fuse Bits Signature Bytes Programming the Flash and EEPROM High-Voltage Serial Programming High-Voltage Serial Programming Algorithm High-Voltage Serial Programming Characteristics Low-Voltage Serial Downloading Low-Voltage Serial Programming Algorithm Data Polling EEPROM Data Polling Flash Low-Voltage Serial Programming Characteristics Electrical Characteristics Absolute Maximum Ratings* DC Characteristics External Clock Drive Waveforms External Clock Drive Typical characteristics Register Summary Instruction Set Summary (Continued) Ordering Information