Datasheet AT90S2323, AT90LS2323, AT90S2343, AT90LS2343 (Atmel) - 10
| 制造商 | Atmel |
| 描述 | 8-bit AVR Microcontroller with 2K Bytes of In-System Programmable Flash |
| 页数 / 页 | 64 / 10 — X-register, Y-register and Zregister The registers R26.R31 have some … |
| 文件格式/大小 | PDF / 1.1 Mb |
| 文件语言 | 英语 |
X-register, Y-register and Zregister The registers R26.R31 have some added functions to their general-purpose usage
该数据表的模型线
文件文字版本
X-register, Y-register and Zregister The registers R26.R31 have some added functions to their general-purpose usage.
These registers are the address pointers for indirect addressing of the Data Space. The
three indirect address registers X, Y, and Z, are defined in Figure 8.
Figure 8. The X-, Y-, and Z-registers
15
X-register 0 7 0 7 R27 ($1B) 0
R26 ($1A) 15
Y-register 0 7 0 7 R29 ($1D) 0
R28 ($1C) 15
Z-register 0 7 0
R31 ($1F) 7 0
R30 ($1E) In the different addressing modes, these address registers have functions as fixed displacement, automatic increment and decrement (see the descriptions for the different
instructions). ALU – Arithmetic Logic
Unit The high-performance AVR ALU operates in direct connection with all the 32 generalpurpose working registers. Within a single clock cycle, ALU operations between registers in the register file are executed. The ALU operations are divided into three main
categories: arithmetic, logic and bit functions. In-System
Programmable Flash
Program Memory The AT90S2323/2343 contains 2K bytes On-chip, In-System Programmable Flash
memory for program storage. Since all instructions are 16-or 32-bit words, the Flash is
organized as 1K x 16. The Flash memory has an endurance of at least 1000 write/erase
cycles.
The AT90S2323/2343 Program Counter (PC) is 10 bits wide, hence addressing the
1024 program memory addresses. See page 42 for a detailed description on Flash data
programming.
Constant tables must be allocated within the address 0 -2K (see the LPM – Load Program Memory instruction description on page 60).
See page 12 for the different addressing modes. EEPROM Data Memory The AT90S2323/2343 contains 128 bytes of EEPROM data memory. It is organized as
a separate data space, in which single bytes can be read and written. The EEPROM has
an endurance of at least 100,000 write/erase cycles. The access between the EEPROM
and the CPU is described on page 32, specifying the EEPROM address register, the
EEPROM data register and the EEPROM control register.
For the SPI data downloading, see page 42 for a detailed description. 10 AT90S/LS2323/2343
1004D–09/01
These registers are the address pointers for indirect addressing of the Data Space. The
three indirect address registers X, Y, and Z, are defined in Figure 8.
Figure 8. The X-, Y-, and Z-registers
15
X-register 0 7 0 7 R27 ($1B) 0
R26 ($1A) 15
Y-register 0 7 0 7 R29 ($1D) 0
R28 ($1C) 15
Z-register 0 7 0
R31 ($1F) 7 0
R30 ($1E) In the different addressing modes, these address registers have functions as fixed displacement, automatic increment and decrement (see the descriptions for the different
instructions). ALU – Arithmetic Logic
Unit The high-performance AVR ALU operates in direct connection with all the 32 generalpurpose working registers. Within a single clock cycle, ALU operations between registers in the register file are executed. The ALU operations are divided into three main
categories: arithmetic, logic and bit functions. In-System
Programmable Flash
Program Memory The AT90S2323/2343 contains 2K bytes On-chip, In-System Programmable Flash
memory for program storage. Since all instructions are 16-or 32-bit words, the Flash is
organized as 1K x 16. The Flash memory has an endurance of at least 1000 write/erase
cycles.
The AT90S2323/2343 Program Counter (PC) is 10 bits wide, hence addressing the
1024 program memory addresses. See page 42 for a detailed description on Flash data
programming.
Constant tables must be allocated within the address 0 -2K (see the LPM – Load Program Memory instruction description on page 60).
See page 12 for the different addressing modes. EEPROM Data Memory The AT90S2323/2343 contains 128 bytes of EEPROM data memory. It is organized as
a separate data space, in which single bytes can be read and written. The EEPROM has
an endurance of at least 100,000 write/erase cycles. The access between the EEPROM
and the CPU is described on page 32, specifying the EEPROM address register, the
EEPROM data register and the EEPROM control register.
For the SPI data downloading, see page 42 for a detailed description. 10 AT90S/LS2323/2343
1004D–09/01