Datasheet ATtiny24, ATtiny44, ATtiny84 (Atmel) - 9

5. CPU Core 5.1 Overview
This section discusses the Atmel® AVR® core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must, therefore, be able to access memories, perform calculations, control peripherals, and handle interrupts.
5.2 Architectural Overview Figure 5-1. Block Diagram of the AVR Architecture
Data Bus 8-bit Program Status and Flash Counter Control Program Memory 32 x 8 General Instruction Purpose Register Registers Interrupt Unit Instruction Watchdog Decoder ALU Timer Analog Control Lines Comparator Direct Addressing Indirect Addressing Timer/Counter 0 Data SRAM Timer/Counter 1 Universal Serial Interface EEPROM I/O Lines In order to maximize performance and parallelism, the AVR uses a Harvard architecture, with separate memories and buses for program and data. Instructions in the program memory are executed with a single-level pipelining. While one instruction is being executed, the next instruction is pre-fetched from the program memory. This concept enables instructions to be executed in every clock cycle. The program memory is in-system reprogrammable flash memory. ATtiny24/44/84 [DATASHEET] 9 7701G–AVR–02/15 Document Outline Features 1. Pin Configurations 1.1 Disclaimer 2. Overview 2.1 Block Diagram 2.2 Automotive Quality Grade 2.3 Pin Descriptions 2.3.1 VCC 2.3.2 GND 2.3.3 Port B (PB3...PB0) 2.3.4 RESET 2.3.5 Port A (PA7...PA0) 3. Resources 4. About Code Examples 5. CPU Core 5.1 Overview 5.2 Architectural Overview 5.3 ALU – Arithmetic Logic Unit 5.4 Status Register 5.4.1 SREG – AVR Status Register 5.5 General Purpose Register File 5.5.1 The X-register, Y-register, and Z-register 5.6 Stack Pointer 5.6.1 SPH and SPL – Stack Pointer High and Low 5.7 Instruction Execution Timing 5.8 Reset and Interrupt Handling 5.8.1 Interrupt Response Time 6. Memories 6.1 In-System Re-programmable Flash Program Memory 6.2 SRAM Data Memory 6.2.1 Data Memory Access Times 6.3 EEPROM Data Memory 6.3.1 EEPROM Read/Write Access 6.3.2 Atomic Byte Programming 6.3.3 Split Byte Programming 6.3.4 Erase 6.3.5 Write 6.3.6 Preventing EEPROM Corruption 6.4 I/O Memory 6.4.1 General Purpose I/O Registers 6.5 Register Description 6.5.1 EEARH – EEPROM Address Register 6.5.2 EEARL – EEPROM Address Register 6.5.3 EEDR – EEPROM Data Register 6.5.4 EECR – EEPROM Control Register 6.5.5 GPIOR2 – General Purpose I/O Register 2 6.5.6 GPIOR1 – General Purpose I/O Register 1 6.5.7 GPIOR0 – General Purpose I/O Register 0 7. System Clock and Clock Options 7.1 Clock Systems and their Distribution 7.1.1 CPU Clock – clkCPU 7.1.2 I/O Clock – clkI/O 7.1.3 Flash Clock – clkFLASH 7.1.4 ADC Clock – clkADC 7.2 Clock Sources 7.3 Default Clock Source 7.4 Crystal Oscillator 7.5 Low-frequency Crystal Oscillator 7.6 Calibrated Internal RC Oscillator 7.7 External Clock 7.8 128kHz Internal Oscillator 7.9 System Clock Prescaler 7.9.1 Switching Time 7.10 Register Description 7.10.1 Oscillator Calibration Register – OSCCAL 7.10.2 Clock Prescaler Register – CLKPR 8. Power Management and Sleep Modes 8.1 Sleep Modes 8.2 Idle Mode 8.3 ADC Noise Reduction Mode 8.4 Power-down Mode 8.5 Standby Mode 8.6 Software BOD Disable 8.7 Power Reduction Register 8.8 Minimizing Power Consumption 8.8.1 Analog-to-Digital Converter 8.8.2 Analog Comparator 8.8.3 Brown-out Detector 8.8.4 Internal Voltage Reference 8.8.5 Watchdog Timer 8.8.6 Port Pins 8.9 Register Description 8.9.1 MCUCR – MCU Control Register 8.9.2 PRR – Power Reduction Register 9. System Control and Reset 9.1 Resetting the AVR 9.2 Reset Sources 9.3 Power-on Reset 9.4 External Reset 9.5 Brown-out Detection 9.6 Watchdog Reset 9.7 Internal Voltage Reference 9.7.1 Voltage Reference Enable Signals and Start-up Time 9.8 Watchdog Timer 9.9 Timed Sequences for Changing the Configuration of the Watchdog Timer 9.9.1 Safety Level 1 9.9.2 Safety Level 2 9.10 Register Description 9.10.1 MCUSR – MCU Status Register 9.10.2 WDTCSR – Watchdog Timer Control and Status Register 10. Interrupts 10.1 Interrupt Vectors 11. External Interrupts 11.1 Pin Change Interrupt Timing 11.2 Register Description 11.2.1 MCUCR – MCU Control Register 11.2.2 GIMSK – General Interrupt Mask Register 11.2.3 GIFR – General Interrupt Flag Register 11.2.4 PCMSK1 – Pin Change Mask Register 1 11.2.5 PCMSK0 – Pin Change Mask Register 0 12. I/O Ports 12.1 Overview 12.2 Ports as General Digital I/O 12.2.1 Configuring the Pin 12.2.2 Toggling the Pin 12.2.3 Switching Between Input and Output 12.2.4 Reading the Pin Value 12.2.5 Digital Input Enable and Sleep Modes 12.2.6 Unconnected Pins 12.3 Alternate Port Functions 12.3.1 Alternate Functions of Port A 12.3.2 Alternate Functions of Port B 12.4 Register Description 12.4.1 MCUCR – MCU Control Register 12.4.2 PORTA – Port A Data Register 12.4.3 DDRA – Port A Data Direction Register 12.4.4 PINA – Port A Input Pins Address 12.4.5 PORTB – Port B Data Register 12.4.6 DDRB – Port B Data Direction Register 12.4.7 PINB – Port BInput Pins Address 13. 8-bit Timer/Counter0 with PWM 13.1 Features 13.2 Overview 13.2.1 Registers 13.2.2 Definitions 13.3 Timer/Counter Clock Sources 13.4 Counter Unit 13.5 Output Compare Unit 13.5.1 Force Output Compare 13.5.2 Compare Match Blocking by TCNT0 Write 13.5.3 Using the Output Compare Unit 13.6 Compare Match Output Unit 13.6.1 Compare Output Mode and Waveform Generation 13.7 Modes of Operation 13.7.1 Normal Mode 13.7.2 Clear Timer on Compare Match (CTC) Mode 13.7.3 Fast PWM Mode 13.7.4 Phase Correct PWM Mode 13.8 Timer/Counter Timing Diagrams 13.9 Register Description 13.9.1 TCCR0A – Timer/Counter Control Register A 13.9.2 TCCR0B – Timer/Counter Control Register B 13.9.3 TCNT0 – Timer/Counter Register 13.9.4 OCR0A – Output Compare Register A 13.9.5 OCR0B – Output Compare Register B 13.9.6 TIMSK0 – Timer/Counter 0 Interrupt Mask Register 13.9.7 TIFR0 – Timer/Counter 0 Interrupt Flag Register 14. 16-bit Timer/Counter1 14.1 Features 14.2 Overview 14.2.1 Registers 14.2.2 Definitions 14.2.3 Compatibility 14.3 Accessing 16-bit Registers 14.3.1 Reusing the Temporary High Byte Register 14.4 Timer/Counter Clock Sources 14.5 Counter Unit 14.6 Input Capture Unit 14.6.1 Input Capture Trigger Source 14.6.2 Noise Canceller 14.6.3 Using the Input Capture Unit 14.7 Output Compare Units 14.7.1 Force Output Compare 14.7.2 Compare Match Blocking by TCNT1 Write 14.7.3 Using the Output Compare Unit 14.8 Compare Match Output Unit 14.8.1 Compare Output Mode and Waveform Generation 14.9 Modes of Operation 14.9.1 Normal Mode 14.9.2 Clear Timer on Compare Match (CTC) Mode 14.9.3 Fast PWM Mode 14.9.4 Phase Correct PWM Mode 14.9.5 Phase and Frequency Correct PWM Mode 14.10 Timer/Counter Timing Diagrams 14.11 Register Description 14.11.1 TCCR1A – Timer/Counter1 Control Register A 14.11.2 TCCR1B – Timer/Counter1 Control Register B 14.11.3 TCCR1C – Timer/Counter1 Control Register C 14.11.4 TCNT1H and TCNT1L – Timer/Counter1 14.11.5 OCR1AH and OCR1AL – Output Compare Register 1 A 14.11.6 OCR1BH and OCR1BL – Output Compare Register 1 B 14.11.7 ICR1H and ICR1L – Input Capture Register 1 14.11.8 TIMSK1 – Timer/Counter Interrupt Mask Register 1 14.11.9 TIFR1 – Timer/Counter Interrupt Flag Register 1 15. Timer/Counter Prescaler 15.1 Prescaler Reset 15.2 External Clock Source 15.3 Register Description 15.3.1 GTCCR – General Timer/Counter Control Register 16. USI – Universal Serial Interface 16.1 Features 16.2 Overview 16.3 Functional Descriptions 16.3.1 Three-wire Mode 16.3.2 SPI Master Operation Example 16.3.3 SPI Slave Operation Example 16.3.4 Two-wire Mode 16.3.5 Start Condition Detector 16.3.6 Clock speed considerations 16.4 Alternative USI Usage 16.4.1 Half-duplex Asynchronous Data Transfer 16.4.2 4-bit Counter 16.4.3 12-bit Timer/Counter 16.4.4 Edge-Triggered External Interrupt 16.4.5 Software Interrupt 16.5 Register Descriptions 16.5.1 USIBR – USI Data Buffer 16.5.2 USIDR – USI Data Register 16.5.3 USISR – USI Status Register 16.5.4 USICR – USI Control Register 17. Analog Comparator 17.1 Analog Comparator Multiplexed Input 17.2 Register Description 17.2.1 ADCSRB – ADC Control and Status Register B 17.2.2 ACSR – Analog Comparator Control and Status Register 17.2.3 DIDR0 – Digital Input Disable Register 0 18. Analog-to-Digital Converter 18.1 Features 18.2 Overview 18.3 ADC Operation 18.4 Starting a Conversion 18.5 Prescaling and Conversion Timing 18.6 Changing Channel or Reference Selection 18.6.1 ADC Input Channels 18.6.2 ADC Voltage Reference 18.7 ADC Noise Canceller 18.7.1 Analog Input Circuitry 18.7.2 Analog Noise Canceling Techniques 18.7.3 ADC Accuracy Definitions 18.8 ADC Conversion Result 18.8.1 Single Ended Conversion 18.8.2 Unipolar Differential Conversion 18.8.3 Bipolar Differential Conversion 18.9 Temperature Measurement 18.10 Register Description 18.10.1 ADMUX – ADC Multiplexer Selection Register 18.10.2 ADCSRA – ADC Control and Status Register A 18.10.3 ADCL and ADCH – ADC Data Register 18.10.3.1 ADLAR = 0 18.10.3.2 ADLAR = 1 18.10.4 ADCSRB – ADC Control and Status Register B 18.10.5 DIDR0 – Digital Input Disable Register 0 19. debugWIRE On-chip Debug System 19.1 Features 19.2 Overview 19.3 Physical Interface 19.4 Software Break Points 19.5 Limitations of debugWIRE 19.6 Register Description 19.6.1 DWDR – debugWire Data Register 20. Self-Programming the Flash 20.1 Performing Page Erase by SPM 20.2 Filling the Temporary Buffer (Page Loading) 20.3 Performing a Page Write 20.4 Addressing the Flash During Self-Programming 20.4.1 EEPROM Write Prevents Writing to SPMCSR 20.4.2 Reading the Lock and Fuse Bits from Software 20.4.3 Preventing Flash Corruption 20.4.4 Programming Time for Flash when Using SPM 20.5 Register Description 20.5.1 SPMCSR – Store Program Memory Control and Status Register 21. Memory Programming 21.1 Program And Data Memory Lock Bits 21.2 Fuse Bytes 21.2.1 Latching of Fuses 21.3 Signature Bytes 21.4 Calibration Byte 21.5 Page Size 21.6 Serial Downloading 21.6.1 Serial Programming Algorithm 21.6.2 Serial Programming Instruction set 21.7 High-voltage Serial Programming 21.8 High-voltage Serial Programming Algorithm 21.8.1 Enter High-voltage Serial Programming Mode 21.8.2 Considerations for Efficient Programming 21.8.3 Chip Erase 21.8.4 Programming the Flash 21.8.5 Programming the EEPROM 21.8.6 Reading the Flash 21.8.7 Reading the EEPROM 21.8.8 Programming and Reading the Fuse and Lock Bits 21.8.9 Reading the Signature Bytes and Calibration Byte 21.8.10 Power-off sequence 22. Electrical Characteristics 22.1 Absolute Maximum Ratings 22.2 Speed Grades 22.3 Clock Characterizations 22.3.1 Calibrated Internal RC Oscillator Accuracy 22.3.2 External Clock Drive Waveforms 22.3.3 External Clock Drive 22.4 System and Reset Characterizations 22.5 ADC Characteristics – Preliminary Data 22.6 Serial Programming Characteristics 22.7 High-voltage Serial Programming Characteristics 23. Typical Characteristics – Preliminary Data 23.1 Active Supply Current 23.2 Idle Supply Current 23.3 Supply Current of IO modules 23.4 Power-down Supply Current 23.5 Pin Pull-up 23.6 Pin Driver Strength 23.7 Pin Threshold and Hysteresis 23.8 BOD Threshold and Analog Comparator Offset 23.9 Internal Oscillator Speed 23.10 Current Consumption of Peripheral Units 23.11 Current Consumption in Reset and Reset Pulse Width 24. Register Summary 25. Instruction Set Summary 26. Ordering Information 26.1 ATtiny24/44/84 27. Packaging Information 27.1 PC 27.2 TU 28. Errata 28.1 ATtiny24 Automotive 28.1.1 Rev. E 28.2 ATtiny44 Automotive 28.2.1 Rev. D 28.3 ATtiny84 Automotive 28.3.1 Rev. B 29. Revision History 30. Table of Contents