Datasheet LTM4677 (Analog Devices) - 31

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operaTion
n Configuring Whether the LTM4677 Pulls SHARE_CLK
POWER MODULE OVERVIEW
Logic Low When SVIN Has Fallen Outside Its UVLO A dedicated remote-sense amplifier precisely kelvin-senses Thresholds (MFR_PWM_CONFIG[4]). MFR_PWM_ V + CONFIG Cannot Be Changed On the Fly; Switching Action OUT0’s load via the differential pin-pair formed by VOSNS0 and V –. V Must Be Off (Uncommon to Alter This Parameter from OSNS0 OUT0 and VOUT1 can be commanded to between 0.5VDC and 1.8VDC. Output voltage readback its NVM-Factory Default Setting). telemetry is available over I2C (READ_VOUTn registers). n Configuring Whether the LTM4677’s Output Voltage Peak output voltage readback telemetry is accessible Digital Servos Are Active vs Disengaged (MFR_PWM_ in the MFR_READ_VOUT_PEAK – n registers. If VOSNS0 MODE + n[6]. Uncommon to Alter This Parameter from exceeds VOSNS , no phase reversal of the differentially- its NVM-Factory Default Settings). sensed output voltage feedback signal occurs (Note 12). Similarly, no phase reversal occurs when SGND exceeds n Configuring Whether the LTM4677’s Current Limit + Range is Set to High Range vs Low Range. (MFR_PWM_ VOSNS1 (Note 12). For added flexibility, the VOSNS0 / – MODE VOSNS0 feedback pins can be configured as the control n[7]. Not Recommended to Alter This Parameter from its NVM-Factory Default Settings). loop feedback path for both VOUT0 and VOUT1 by setting MFR_PWM_CONFIG[7]=1b. (See Figure 27). Remaining LTM4677 status that can be queried over I2C communications follow: The typical application schematic is shown in Figure 56 on the back page of this data sheet. n Access to Three “Hand-Shaking” Status Bits (MFR_COMMON[6:4]) to Ease Implementation of The LTM4677 can operate from input voltages between PMBus Busy Protocols, i.e., Enabling Fast and Robust 5.75V and 16V (see front page figure). In this con- System Level Communication Through Polling of These figuration, INTVCC MOSFET driver and control IC bias is Bits to Infer LTM4677’s Readiness to Act on Subsequent generated internally by an LDO fed from SVIN to produce I2C Writes. (See PMBus Communication and Command 5V at up to 100mA peak output current. Additional in- Processing, in the Applications Information Section.) ternal LDOs—3.3V (VDD33), derived from INTVCC, and 2.5V (VDD25), derived from VDD33—bias the LTM4677’s n Providing a Means to Determine Whether the LTM4677 digital circuitry. When INTVCC is connected to SVIN, the NVM Download to RAM Has Occurred (“NVM Initial- LTM4677 can operate from input voltages between 4.5V ized”, MFR_COMMON[3]). and 5.75V (see Figure 27). Control IC bias (SVIN) is routed independent of the inputs to the power stages (V n Providing a Means Other Than ARA Protocol to De- IN0, VIN1); termine Whether the LTM4677 is Pulling ALERT Low this enables step-down DC/DC conversion from less than (MFR_COMMON[7]). 4.5V input (see Figure 28), so long as auxiliary power (4.5V ~ 16V) is available to bias the control IC appropri- n Detecting a SHARE_CLK T imeout Event ately. Furthermore, the inputs of the two power stages are (MFR_COMMON[1]). not connected together internal to the module; therefore, n Verifying or Altering the Slave Address of the LTM4677 DC/DC step-down conversion from two different source (MFR_ADDRESS). power supplies can be performed. Per Note 6 of the Electrical Characteristics section, the output current may require derating for some operating scenarios. Detailed derating guidance is provided in the Applications Information section. 4677fa For more information www.linear.com/LTM4677 31 Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Order Information Pin Configuration Electrical Characteristics Typical Performance Characteristics Pin Functions Simplified Block Diagram Decoupling Requirements Functional Diagram Test Circuits Operation Power Module Introduction Power Module Configurability and Readback Data Time-Averaged and Peak Readback Data Power Module Overview EEPROM Serial Interface Device Addressing Fault Detection and Handling Responses to VOUT and IOUT Faults Responses to Timing Faults Responses to SVIN OV Faults Responses to OT/UT Faults Responses to External Faults Fault Logging Bus Timeout Protection PMBus Command Summary PMBus Commands Applications Information VIN to VOUT Step-Down Ratios Input Capacitors Output Capacitors Light Load Current Operation Switching Frequency and Phase Minimum On-Time Considerations Variable Delay Time, Soft-Start and Output Voltage Ramping Digital Servo Mode Soft Off (Sequenced Off) Undervoltage Lockout Fault DETECTION AND HANDLING Open-Drain Pins Phase-Locked Loop and Frequency Synchronization RCONFIG Pin-Straps (External Resistor Configuration Pins) Voltage Selection Connecting the USB to the I2C/SMBus/PMBus Controller to the LTM4677 In System PMBus Communication and Command Processing Thermal Considerations and Output Current Derating Applications Information-Derating Curves EMI Performance Safety Considerations Layout Checklist/Example Typical Applications Appendix A Similarity Between PMBus, SMBus and I2C 2-Wire Interface Appendix B PMBus Serial Digital Interface Appendix C: PMBus Command Details Addressing and Write Protect General Configuration Registers On/Off/Margin PWM Config Voltage Current Temperature Timing Fault Response Fault Sharing Scratchpad Identification Fault Warning and Status Telemetry NVM (EEPROM) Memory Commands Package Description Package Photograph Revision History Typical Application Design Resources Related Parts