Datasheet LTM4633 (Analog Devices) - 7

LTM4633
pin FuncTions PACKAGE ROW AND COLUMN LABELING MAY VARY CNTL_PWR (J6):
Input Supply to an Internal Bias LDO to
AMONG µModule PRODUCTS. REVIEW EACH PACKAGE LAYOUT CAREFULLY.
Power the Internal Controller and MOSFET Drivers. This pin is connected to an input supply voltage range of 4.7V
GND (A4, A8-A9, D1- D12, E1-E12, F4, F8, F12, G3-G4,
to 16V. If the voltage at CNTL_PWR is ≤5.5V, the INTVCC
G7-G8, G11-G12, H3-H4, H7-H8, H11-H12, J1-J5, J7,
pin should be tied to CNTL_PWR for optimum efficiency.
J9-J12, K1-K3, K8-K10, K12,L1-L2,L12, M1, M6-M8,
If the voltage at CNTL_PWR is >5.5V, leave INTVCC floating
M12):
Ground Pins for Both Input and Output Returns. with the recommended decoupling capacitor. When using All ground pins need to connect with large copper areas multiple input supplies, choose the lowest input supply underneath the unit. between 4.7V to 16V to supply the CNTL_PWR pin. This
V
will lower the internal power loss and improve efficiency.
OUT1, VOUT2, VOUT3 (A10-A12, B9-B12, and C10-C12); (A5-A7, B5-B8, C6-C8); (A1-A3, B1-B4, C1-C4):
Power
INTVCC (J8):
Output of the Internal Bias LDO for Powering Output Pins. Apply output load between these pins and Internal Control Circuitry. Connect a 4.7µF ceramic capaci- the GND pins. Recommend placing output decoupling tor to ground for decoupling. If the voltage at CNTL_PWR capacitance directly between these pins and the GND is ≤5.5V, tie the INTVCC pin to CNTL_PWR for optimum pins. See Table 5. efficiency. If the voltage at CNTL_PWR is >5.5V, leave
TEMP1 AND TEMP2 (C9, C5):
Two Onboard Temperature INTVCC floating. See the Applications Information section. Diodes for Monitoring the VBE Junction Voltage Change
SGND (K6-K7, L6-L7):
Signal Ground Connections. The with Temperature. Each of these two temperature diode signal ground connection in the module is separated from connected PNP transistors is placed in the middle of normal power ground (GND) by an internal 2.2Ω resistor. channel 1 and channel 2, and in the middle of channel 2 This allows the designer to connect the signal ground pin and channel 3. See the Applications Information section close to GND near the external output capacitors on the and an example in Figure 19. regulator channel’s outputs. The entire internal small-signal
V
feedback circuitry is referenced to SGND, thus allowing
IN1,VIN2,VIN3 (F9-F10,G9-G10,H9-H10);(F5-F6,G5- G6,H5-H6);(F1-F2,G1-G2,H1-H2):
Power Input Pins. for better output regulation. See the recommended layout Apply input voltage between these pins and the GND pins. in the Applications Information section. Recommend placing input decoupling capacitance directly
EXTVCC (L3):
External Bias Power Input. The internal bias between the VIN pins and the GND pins. The VIN paths LDO is bypassed whenever the voltage at EXTVCC is above can be all combined from one power source, or powered 4.7V. Never exceed 6V at this pin and ensure CNTL_PWR > from independent power sources. The VIN paths can EXTVCC at all times to avoid reverse polarity on the internal operate down to 2.375V when the CNTL_PWR is biased bias LDO. Connect a 1µF capacitor to ground when used separately from a supply in the range of 4.7V to 16V. See otherwise leave floating. When generating a 5V output on the Applications Information section. channel 3, connect the 5V output to this pin to improve
SW1 (F11), SW2 (F7), SW3 (F3):
The internal switch efficiency. node for each of the regulator channels for monitoring the switching waveform. An R-C snubber circuit can be placed on these pins to ground to eliminate switch node ringing noise. 4633f For more information www.linear.com/LTM4633 7 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information Typical Applications Related Parts