Datasheet LTM4612 (Analog Devices) - 7

LTM4612
PIN FUNCTIONS (See Package Description for Pin Assignments) VIN (Bank 1):
Power Input Pins. Apply input voltage be-
FCB (Pin M12):
Forced Continuous Input. Connect this pin tween these pins and PGND pins. Recommend placing to SGND to force continuous synchronization operation at input decoupling capacitance directly between VIN pins low load, to INTVCC to enable discontinuous mode opera- and PGND pins. tion at low load or to a resistive divider from a secondary
PGND (Bank 2):
Power Ground Pins for Both Input and output when using a secondary winding. Output Returns.
TRACK/SS (Pin A9):
Output Voltage Tracking and Soft-Start
V
Pin. When the module is configured as a master output,
OUT (Bank 3):
Power Output Pins. Apply output load between these pins and PGND pins. Recommend placing out- then a soft-start capacitor is placed on this pin to ground put decoupling capacitance directly between these pins and to control the master ramp rate. A soft-start capacitor can GND pins (see the LTM4612 Pin Configuration below). be used for soft-start turn-on as a standalone regulator. Slave operation is performed by putting a resistor divider
VD (Pins B7, C7):
Top FET Drain Pins. Add more capa- from the master output to the ground, and connecting the citors between VD and ground to handle the input RMS center point of the divider to this pin. See the Applications current and reduce the input ripple further. Information section.
DRVCC (Pins C10, E11, E12):
These pins normally connect
MPGM (Pins A12, B11):
Programmable Margining In- to INTVCC for powering the internal MOSFET drivers. They put. A resistor from these pins to ground sets a current can be biased up to 6V from an external supply with about that is equal to 1.18V/R. This current multiplied by 10k 50mA capability. This improves efficiency at higher input will equal a value in millivolts that is a percentage of the voltages by reducing power dissipation in the module. 0.6V reference voltage. May be left open if margining is
INTVCC (Pin A7):
This pin is for additional decoupling of not desired. See the Applications Information section. To the 5V internal regulator. parallel LTM4612s, each requires an individual MPGM resistor. Do not tie MPGM pins together.
PLLIN (Pin A8):
External Clock Synchronization Input to the Phase Detector. This pin is internally terminated to SGND
fSET (Pin B12):
Frequency Set Internally to ~850kHz to with a 50k resistor. Apply a clock above 2V and below 900kHz at 12V Output. An external resistor can be placed INTVCC. See the Applications Information section. from this pin to ground to increase frequency. See the Applications Information section for frequency adjustment. TOP VIEW V CC INT PLLIN TRACK/SS RUN COMP MPGM A VIN B f BANK 1 V SET D C MARG0 SGND D MARG1 E DRVCC PGND F VFB BANK 2 G PGOOD H SGND J NC VOUT K NC BANK 3 L NC M FCB 1 2 3 4 5 6 7 8 9 10 11 12 LGA PACKAGE 133-LEAD (15mm × 15mm × 2.8mm)
LTM4612 Pin Configuration
4612fc For more information www.linear.com/LTM4612 7 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Decoupling Requirements Operation Applications Information Package Description Revision History Package Photograph Related Parts