Datasheet LTM4616 (Analog Devices) - 7

LTM4616
pin Functions VIN1, VIN2, (BANK1 and BANK2); (F1-F4, E1-E4, C1-C2, PLLLPF1 and PLLLPF2 (E6 and L6):
Phase-Locked Loop
D1-D2) and (J1-J2, K1-K2, L1-L4, M1-M4):
Power Input Lowpass Filter for Each Channel. An internal lowpass filter Pins. Apply input voltage between these pins and GND is tied to this pin. In spread spectrum mode, placing a pins. Recommend placing input decoupling capacitance capacitor here to SGND controls the slew rate from one directly between V frequency to the next. Alternatively, floating this pin allows IN pins and GND pins. normal running frequency at 1.5MHz, tying this pin to SVIN
VOUT1, VOUT2 (BANK3 and BANK6); (D9-D12, E9-E12,
forces the part to run at 1.33 times its normal frequency
F9-F12) and (K9-K12, L9-L12, M9-M12):
Power Output (2MHz), tying it to ground forces the frequency to run at Pins. Apply output load between these pins and GND 0.67 times its normal frequency (1MHz). pins. Recommend placing output decoupling capacitance directly between these pins and GND pins. See Table 1.
PHMODE1 and PHMODE2 (A9 and G9):
Phase Selector Input for Each Channel. This pin determines the phase
GND1 and GND2 (BANK2 and BANK5); (A1-A5, A12, B1-
relationship between the internal oscillator and CLKOUT.
B5, B7-B12, C3-C12, D3-D7) and (G1-G5, G12, H1-H5,
Tie it high for 2-phase operation, tie it low for 3-phase
H7-H12, J3-J12, K3-K7):
Power Ground Pins for Both operation, and float or tie it to VIN/2 for 4-phase operation. Input and Output Returns.
MGN1 and MGN2 (A10 and G10):
Voltage Margining
SVIN1 and SVIN2 (E5 and L5):
Signal Input Voltage for Each Pin for Each Channel. Increases or decreases the output Channel. This pin is internally connected to VIN through voltage by the amount specified by the BSEL pin. To a lowpass filter. disable margining, tie the MGN pin to a voltage divider
SGND1 and SGND2 (F5 and M5):
Signal Ground Pin for with 50k resistors from VIN to ground (see Figure 5). Each Channel. Return ground path for all analog and low For margining, connect a voltage divider from VIN to GND power circuitry. Tie a single connection to the output with the center point connected to the MGN pin for the spe- capacitor GND in the application. See layout guidelines cific channel. Each resistor should be close to 50k. Margin in Figure 17. High is within 0.3V of VIN, and Margin Low is within 0.3V of GND. See the Applications Information section and Figure
MODE1 and MODE2 (A8 and G8):
Mode Select Input for 18 for margining control. The specified tri-state drivers are Each Channel. Tying this pin high enables Burst Mode capable of the high and low requirements for margining. operation. Tying this pin low enables forced continuous operation. Floating this pin or tying it to V
BSEL1 and BSEL2 (A6 and G6):
Margining Bit Select Pin IN/2 enables pulse-skipping operation. for Each Channel. Tying BSEL low selects ±5% margin value, tying it high selects 10% margin value. Floating it
CLKIN1 and CLKIN2 (A7 and G7):
External Synchroniza- or tying it to VIN/2 selects 15% margin value. tion Input to Phase Detector for Each Channel. This pin is internally terminated to SGND with a 50k resistor. The
TRACK1 and TRACK2 (E8 and L8):
Output Voltage Tracking phase-locked loop will force the internal top power PMOS Pin for Each Channel. Voltage tracking is enabled when the turn on to be synchronized with the rising edge of the TRACK voltage is below 0.57V. If tracking is not desired, CLKIN signal. Connect this pin to SV then connect the TRACK pin to SV IN to enable spread IN. If TRACK is not tied spectrum modulation. During external synchronization, to SVIN, then the TRACK pin’s voltage needs to be below make sure the PLLLPF pin is not tied to V 0.18V before the chip shuts down even though RUN is IN or GND. 4616ff For more information www.linear.com/LTM4616 7 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Pin Functions Simplified Block Diagram Operation Applications Information Package Description Revision History Package Photo Related Parts Design Resources