Datasheet LTC4366 (Analog Devices) - 8
| 制造商 | Analog Devices |
| 描述 | High Voltage Surge Stopper |
| 页数 / 页 | 24 / 8 — PIN FUNCTIONS BASE:. SD:. Exposed Pad:. FB:. GATE:. TIMER:. VDD:. OUT:. … |
| 文件格式/大小 | PDF / 298 Kb |
| 文件语言 | 英语 |
PIN FUNCTIONS BASE:. SD:. Exposed Pad:. FB:. GATE:. TIMER:. VDD:. OUT:. VSS:
该数据表的模型线
- LTC4366CDDB-1#PBF LTC4366CDDB-1#TRMPBF LTC4366CDDB-1#TRPBF LTC4366CDDB-2#PBF LTC4366CDDB-2#TRMPBF LTC4366CDDB-2#TRPBF LTC4366CTS8-1#PBF LTC4366CTS8-1#TRMPBF LTC4366CTS8-1#TRPBF LTC4366CTS8-2#PBF LTC4366CTS8-2#TRMPBF LTC4366CTS8-2#TRPBF LTC4366HDDB-1#PBF LTC4366HDDB-1#TRMPBF LTC4366HDDB-1#TRPBF LTC4366HDDB-2#PBF LTC4366HDDB-2#TRMPBF LTC4366HDDB-2#TRPBF LTC4366HTS8-1#PBF LTC4366HTS8-1#TRMPBF LTC4366HTS8-1#TRPBF LTC4366HTS8-2#PBF LTC4366HTS8-2#TRMPBF LTC4366HTS8-2#TRPBF LTC4366IDDB-1#PBF LTC4366IDDB-1#TRMPBF LTC4366IDDB-1#TRPBF LTC4366IDDB-2#PBF LTC4366IDDB-2#TRMPBF LTC4366IDDB-2#TRPBF LTC4366ITS8-1#PBF LTC4366ITS8-1#TRMPBF LTC4366ITS8-1#TRPBF LTC4366ITS8-2#PBF LTC4366ITS8-2#TRMPBF LTC4366ITS8-2#TRPBF LTC4366MPDDB-1#PBF LTC4366MPDDB-1#TRMPBF LTC4366MPDDB-1#TRPBF LTC4366MPDDB-2#PBF LTC4366MPDDB-2#TRMPBF LTC4366MPDDB-2#TRPBF LTC4366MPTS8-1#PBF LTC4366MPTS8-1#TRMPBF LTC4366MPTS8-1#TRPBF LTC4366MPTS8-2#PBF LTC4366MPTS8-2#TRM LTC4366MPTS8-2#TRMPBF LTC4366MPTS8-2#TRPBF
文件文字版本
LTC4366
PIN FUNCTIONS BASE:
Base Driver Output for External PNP Shunt Regula-
SD:
Shutdown Comparator Input. Tie to VDD if unused. tor. This pin is connected to the anode of an internal 6.2V Connect pin to a limited current pull down created by adding Zener with the cathode tied to OUT. In cases where lower a resistor in series with an open-drain or open-collector Zener (Z3) clamp current is desired but a large VSS resis- pull-down transistor. Activating the external pull down tor is prohibited, connect an external PNP base to this pin overcomes the internal 1.6µA pull-up current source and (PNP collector is grounded, emitter is tied to VSS). Tie this allows the SD pin to cross the shutdown threshold. This pin to VSS if unused. threshold is defined as 1.5V below VDD with a 280mV
Exposed Pad:
The exposed pad may be left open or con- hysteresis. To prevent false triggers this pin must stay nected to V below the threshold for 700µs to activate the shutdown SS. state. The shutdown state lowers the total quiescent cur-
FB:
Overvoltage Regulation Amplifier Feedback Input. rent (IVDD plus IOUT) below 20µA. This quiescent current Connect this pin to an external resistive divider from OUT does not include shunt current in the VDD, OUT and BASE to ground. The overvoltage regulation amplifier controls regulators. After a fault on the LTC4366, putting the part the gate of the external N-channel MOSFET to regulate in shutdown will clear the fault and allow operation to the FB pin voltage at 1.23V below OUT. The overvoltage resume. Clearing the fault during the 9-second cool-down amplifier will activate a 200mA pull-down on the GATE pin period will shorten the timeout for the LTC4366-2 (auto- during a fast overvoltage event. retry) version.
GATE:
Gate Drive for External N-Channel MOSFET. Dur-
TIMER:
Timer Input. Leave this pin open for a 1µs overvolt- ing start-up an internal 7.5µA current source charges the age regulation period before fault off. Connect a capacitor gate of the external N-channel MOSFET from the VDD pin. between this pin and VSS to set a 311ms/µF duration for Once the OUT voltage is above VSS by 4.75V, the charge overvoltage regulation before the switch is turned off. pump will finish charging the GATE to 12V above OUT. The LTC4366-2 version will restart after a nine second During a fast overvoltage event, a 200mA pull-down cur- cool-down period. rent source between GATE and OUT is activated, followed by regulation of the GATE pin voltage by the overvoltage
VDD:
Start-Up Supply. Supply input for 7.5µA start-up cur- regulation amplifier. rent source that charges the gate of the external N-channel MOSFET. Also provides supply for timer and logic circuits
OUT:
Charge Pump and Overvoltage Regulation Amplifier active when the external MOSFET is off. This pin is clamped Supply Voltage. Supply input for floating circuitry powered at 12V above VSS. Do not bypass this pin with a capacitor. from the MOSFET source. Once the OUT voltage is 4.75V (UVLO2) above V
VSS:
Device Return and Substrate. The capacitors on the SS, the charge pump will turn on and draw power from this pin. When OUT exceeds 2.55V (UVLO1) TIMER and OUT pins should be returned to this pin. it is used as a power supply and reference input for over- voltage regulation amplifier. This pin is clamped at 5.7V and requires a 0.22µF or greater bypass to the VSS pin. 436612fe 8 For more information www.linear.com/LTC4366 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Pin Functions Simplified Diagram Functional Diagram Operation Applications Information Package Description Typical Application Related Parts
PIN FUNCTIONS BASE:
Base Driver Output for External PNP Shunt Regula-
SD:
Shutdown Comparator Input. Tie to VDD if unused. tor. This pin is connected to the anode of an internal 6.2V Connect pin to a limited current pull down created by adding Zener with the cathode tied to OUT. In cases where lower a resistor in series with an open-drain or open-collector Zener (Z3) clamp current is desired but a large VSS resis- pull-down transistor. Activating the external pull down tor is prohibited, connect an external PNP base to this pin overcomes the internal 1.6µA pull-up current source and (PNP collector is grounded, emitter is tied to VSS). Tie this allows the SD pin to cross the shutdown threshold. This pin to VSS if unused. threshold is defined as 1.5V below VDD with a 280mV
Exposed Pad:
The exposed pad may be left open or con- hysteresis. To prevent false triggers this pin must stay nected to V below the threshold for 700µs to activate the shutdown SS. state. The shutdown state lowers the total quiescent cur-
FB:
Overvoltage Regulation Amplifier Feedback Input. rent (IVDD plus IOUT) below 20µA. This quiescent current Connect this pin to an external resistive divider from OUT does not include shunt current in the VDD, OUT and BASE to ground. The overvoltage regulation amplifier controls regulators. After a fault on the LTC4366, putting the part the gate of the external N-channel MOSFET to regulate in shutdown will clear the fault and allow operation to the FB pin voltage at 1.23V below OUT. The overvoltage resume. Clearing the fault during the 9-second cool-down amplifier will activate a 200mA pull-down on the GATE pin period will shorten the timeout for the LTC4366-2 (auto- during a fast overvoltage event. retry) version.
GATE:
Gate Drive for External N-Channel MOSFET. Dur-
TIMER:
Timer Input. Leave this pin open for a 1µs overvolt- ing start-up an internal 7.5µA current source charges the age regulation period before fault off. Connect a capacitor gate of the external N-channel MOSFET from the VDD pin. between this pin and VSS to set a 311ms/µF duration for Once the OUT voltage is above VSS by 4.75V, the charge overvoltage regulation before the switch is turned off. pump will finish charging the GATE to 12V above OUT. The LTC4366-2 version will restart after a nine second During a fast overvoltage event, a 200mA pull-down cur- cool-down period. rent source between GATE and OUT is activated, followed by regulation of the GATE pin voltage by the overvoltage
VDD:
Start-Up Supply. Supply input for 7.5µA start-up cur- regulation amplifier. rent source that charges the gate of the external N-channel MOSFET. Also provides supply for timer and logic circuits
OUT:
Charge Pump and Overvoltage Regulation Amplifier active when the external MOSFET is off. This pin is clamped Supply Voltage. Supply input for floating circuitry powered at 12V above VSS. Do not bypass this pin with a capacitor. from the MOSFET source. Once the OUT voltage is 4.75V (UVLO2) above V
VSS:
Device Return and Substrate. The capacitors on the SS, the charge pump will turn on and draw power from this pin. When OUT exceeds 2.55V (UVLO1) TIMER and OUT pins should be returned to this pin. it is used as a power supply and reference input for over- voltage regulation amplifier. This pin is clamped at 5.7V and requires a 0.22µF or greater bypass to the VSS pin. 436612fe 8 For more information www.linear.com/LTC4366 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Pin Functions Simplified Diagram Functional Diagram Operation Applications Information Package Description Typical Application Related Parts