Datasheet LTC4162-S (Analog Devices) - 5
| 制造商 | Analog Devices |
| 描述 | 35V/3.2A Lead-Acid Step-Down Battery Charger with PowerPath and I2C Telemetry |
| 页数 / 页 | 46 / 5 — ELECTRICAL CHARACTERISTICS. The. denotes the specifications which apply … |
| 修订版 | B |
| 文件格式/大小 | PDF / 1.0 Mb |
| 文件语言 | 英语 |
ELECTRICAL CHARACTERISTICS. The. denotes the specifications which apply over the full specified
文件文字版本
link to page 42 LTC4162-S
ELECTRICAL CHARACTERISTICS The
l
denotes the specifications which apply over the full specified operating junction temperature range, otherwise specifications are at TA = 25°C (Note 4). VIN = 18V, DVCC = 3.3V, RSNSI = 10mΩ, RSNSB = 10mΩ unless otherwise noted. SYMBOL
PARAMETER CONDITIONS
MIN TYP MAX UNITS Telemetry A/D Measurement Subsystem
IBAT Resolution IBAT = (VCSP – VCSN)/RSNSB 1.466 µV /LSB (VCSP – VCSN) Offset Error 0.32mV < VCSP – VCSN < 32mV –0.15 0.15 mV Span Error –1 1 %rdng IIN Resolution IIN = (VCLP – VCLN)/RSNSI 1.466 µV/LSB (VCLP – VCLN) Offset Error 0.32mV < VCLP – VCLN < 32mV –0.15 0.15 mV Span Error –1 1 %rdng VIN Resolution 1.649 mV/LSB Offset Error 3V < VIN < 35V –25 25 mV Span Error –1 1 %rdng VBATSENS+ Resolution 192.4 µV/LSB (Per 6V Battery) Offset Error 2V < VBATSENS+ < 7.8V –10 10 mV Span Error –1 1 %rdng VOUT Resolution 1.653 mV/LSB Offset Error 3V < VOUT < 35V –25 25 mV Span Error –1 1 %rdng VNTC/VNTCBIAS Resolution 45.833 µV/V/LSB Offset Error 0 < VNTC/VNTCBIAS < 1 –1 1 mV/V Span Error –1 1 %rdng T_die Resolution 0.0215 °C/LSB Offset –264.4 °C
Serial Port, SDA, SCL, SMBALERT
DVCC Logic Reference Level l 1.8 5.5 V IDVCCQ DVCC Current SCL/SDA = DVCC, 0kHz 0 µA ADDRESS I2C Address 0b1101000[R/W] VIHI2C Input High Threshold 70 % DVCC VILI2C Input Low Threshold 30 % DVCC VOLI2C Digital Output Low (SDA/SCL/SMBALERT) ISDA/SCL/SMBALERT = 3mA 400 mV FSCL SCL Clock Frequency 400 kHz tLOW LOW Period of SCL Clock 1.3 µs tHIGH HIGH Period of SCL Clock 0.6 µs tBUF Bus Free Time Between Start and Stop 1.3 µs Conditions tHD,STA Hold Time, After (Repeated) Start 0.6 µs Condition tSU,STA Setup Time after a Repeated Start 0.6 µs Condition tSU,STO Stop Condition Set-Up Time 0.6 µs tHD,DAT(OUT) Output Data Hold Time 0 900 ns tHD,DAT(IN) Input Data Hold Time 0 ns tSU,DAT Data Set-Up Time 100 ns tSP Input Spike Suppression Pulse Width 50 ns Rev 0 For more information www.analog.com 5 Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Order Information Pin Configuration Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram ESD Diagram Timing Diagram Operation Applications Information Register Descriptions Typical Applications Package Description Typical Application Related Parts
ELECTRICAL CHARACTERISTICS The
l
denotes the specifications which apply over the full specified operating junction temperature range, otherwise specifications are at TA = 25°C (Note 4). VIN = 18V, DVCC = 3.3V, RSNSI = 10mΩ, RSNSB = 10mΩ unless otherwise noted. SYMBOL
PARAMETER CONDITIONS
MIN TYP MAX UNITS Telemetry A/D Measurement Subsystem
IBAT Resolution IBAT = (VCSP – VCSN)/RSNSB 1.466 µV /LSB (VCSP – VCSN) Offset Error 0.32mV < VCSP – VCSN < 32mV –0.15 0.15 mV Span Error –1 1 %rdng IIN Resolution IIN = (VCLP – VCLN)/RSNSI 1.466 µV/LSB (VCLP – VCLN) Offset Error 0.32mV < VCLP – VCLN < 32mV –0.15 0.15 mV Span Error –1 1 %rdng VIN Resolution 1.649 mV/LSB Offset Error 3V < VIN < 35V –25 25 mV Span Error –1 1 %rdng VBATSENS+ Resolution 192.4 µV/LSB (Per 6V Battery) Offset Error 2V < VBATSENS+ < 7.8V –10 10 mV Span Error –1 1 %rdng VOUT Resolution 1.653 mV/LSB Offset Error 3V < VOUT < 35V –25 25 mV Span Error –1 1 %rdng VNTC/VNTCBIAS Resolution 45.833 µV/V/LSB Offset Error 0 < VNTC/VNTCBIAS < 1 –1 1 mV/V Span Error –1 1 %rdng T_die Resolution 0.0215 °C/LSB Offset –264.4 °C
Serial Port, SDA, SCL, SMBALERT
DVCC Logic Reference Level l 1.8 5.5 V IDVCCQ DVCC Current SCL/SDA = DVCC, 0kHz 0 µA ADDRESS I2C Address 0b1101000[R/W] VIHI2C Input High Threshold 70 % DVCC VILI2C Input Low Threshold 30 % DVCC VOLI2C Digital Output Low (SDA/SCL/SMBALERT) ISDA/SCL/SMBALERT = 3mA 400 mV FSCL SCL Clock Frequency 400 kHz tLOW LOW Period of SCL Clock 1.3 µs tHIGH HIGH Period of SCL Clock 0.6 µs tBUF Bus Free Time Between Start and Stop 1.3 µs Conditions tHD,STA Hold Time, After (Repeated) Start 0.6 µs Condition tSU,STA Setup Time after a Repeated Start 0.6 µs Condition tSU,STO Stop Condition Set-Up Time 0.6 µs tHD,DAT(OUT) Output Data Hold Time 0 900 ns tHD,DAT(IN) Input Data Hold Time 0 ns tSU,DAT Data Set-Up Time 100 ns tSP Input Spike Suppression Pulse Width 50 ns Rev 0 For more information www.analog.com 5 Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Order Information Pin Configuration Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram ESD Diagram Timing Diagram Operation Applications Information Register Descriptions Typical Applications Package Description Typical Application Related Parts