Datasheet LTC4162-S (Analog Devices) - 10

LTC4162-S
PIN FUNCTIONS BOOST (Pin 1):
Gate-Drive bias for the high side switch in
NTCBIAS (Pin 9):
NTC thermistor bias output. Connect a the switching regulator. This pin provides a pumped bias low temperature coefficient bias resistor between NTCBIAS voltage relative to SW. The voltage on this pin is charged and NTC, and a thermistor between NTC and GND. The up through an internal diode from INTVCC. A 22nF multi- bias resistor should be equal in value to the nominal value layer ceramic capacitor is required from SW to BOOST. of the thermistor. The LTC4162 applies 1.2V to this pin
INTV
during NTC measurement and expects a thermistor β
CC (Pin 2):
Bypass pin for the internal 5V regulator. This regulator provides power to the internal analog cir- value of 3490K. Higher β value thermistors can be used cuitry. A 4.7µF multilayer ceramic capacitor is required with simple circuit modifications. from INTVCC to GND.
NTC (Pin 10):
Thermistor input. The NTC pin connects to
V
a negative temperature coefficient thermistor to monitor
OUTA (Pin 3):
Analog system power pin. VOUTA powers the majority of circuits on the LTC4162. A 0.1µF multilayer the temperature of the battery. The voltage on this pin ceramic capacitor is required from V is digitized by the analog to digital converter to qualify OUTA to GND. battery charging and is available for readout via the I2C
CLN (Pin 4):
Connection point for the negative terminal port. A low drift bias resistor is required from NTCBIAS of the sense resistor that measures and regulates input to NTC and a thermistor is required from NTC to ground. current by limiting charge current.
RT (Pin 11):
Switching regulator frequency control pin.
CLP (Pin 5):
Connection point for the positive terminal The RT pin controls the switching regulator's internal of the sense resistor that measures and regulates input oscillator frequency by placing a resistor from RT to GND. current by limiting charge current.
SMBALERT (Pin 12):
Interrupt output. This open drain
INFET (Pin 6):
Gate control output pin for an input reverse output pulls low when one or more of the programmable blocking external N-channel MOSFET between VIN and alerts is triggered. VOUT.
SCL (Pin 13):
Open drain clock input for the I2C port. The
VIN (Pin 7):
Supply voltage detection and INFET charge I2C port input levels are scaled with respect to DVCC for pump supply for the INFET/BATFET PowerPath. When I2C compliance. voltage at VIN is detected as being high enough to charge a battery, the INFET charge-pump is activated and the BATFET
SDA (Pin 14):
Open drain data input/output for the I2C charge-pump is deactivated thereby powering V port. The I2C port input levels are scaled with respect to OUTA from the input supply through an external NMOS transistor and DVCC for I2C compliance. also starting a charge cycle. A 0.1µF multilayer ceramic
DVCC (Pin 15):
Logic supply for the I2C port. DVCC sets the capacitor is required from VIN to GND. reference level of the SDA and SCL pins for I2C compli-
VCC2P5 (Pin 8):
Bypass pin for the internal 2.5V regula- ance. It should be connected to the same power supply tor. This regulator provides power to the internal logic as the SDA and SCL pull up resistors. circuitry. A 1µF multilayer ceramic capacitor is required
SYNC (Pin 16):
Optional external clock input for the switch- from VCC2P5 to GND. ing battery charger. The switching battery charger will lock to a square wave or pulse on this pin that is close to the frequency programmed by the RT pin. Ground SYNC if this feature is not needed. Rev 0 10 For more information www.analog.com Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Order Information Pin Configuration Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram ESD Diagram Timing Diagram Operation Applications Information Register Descriptions Typical Applications Package Description Typical Application Related Parts