Datasheet LTC4101 (Analog Devices) - 5
| 制造商 | Analog Devices |
| 描述 | Smart Battery Charger Controller |
| 页数 / 页 | 30 / 5 — ELECTRICAL CHARACTERISTICS. The. denotes the specifi cations which apply … |
| 文件格式/大小 | PDF / 261 Kb |
| 文件语言 | 英语 |
ELECTRICAL CHARACTERISTICS. The. denotes the specifi cations which apply over the full operating
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LTC4101
ELECTRICAL CHARACTERISTICS The
l
denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. VDCIN = 20V, VDD = 3.3V, VBAT = 4V unless otherwise noted. (Note 4) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Logic Levels
VIL SCL/SDA Input Low Voltage VDD = 3V and VDD = 5.5V l 0.8 V VIH SCL/SDA Input High Voltage VDD = 3V and VDD = 5.5V l 2.1 V VOL SDA Output Low Voltage IPULL-UP = 350μA l 0.4 V IIL SCL/SDA Input Current VSDA, VSCL = VIL –1 1 μA IIH SCL/SDA Input Current VSDA, VSCL = VIH –1 1 μA VOL SMBALERT Output Low Voltage IPULL-UP = 500μA l 0.4 V SMBALERT Output Pull-Up Current VSMBALERT = VOL –17.5 –10 –3.5 μA ILEAK SDA/SCL/SMBALERT Power Down Leakage VSDA, VSCL, VSMBALERT = 5.5V, VDD = OV l –2 2 μA VOL CHGEN Output Low Voltage IOL = 100μA l 0.5 V CHGEN Output Pull-Up Current VCHGEN = VOL –17.5 –10 –3.5 μA VIL CHGEN Input Low Voltage l 0.9 V VIH CHGEN Input High Voltage VDD = 3V l 2.5 V VDD = 5.5V 3.9 V Power-On Reset Duration VDD Ramp from 0V to >3V in <5μs 100 μs
SMBus Timing (Refer to System Management Bus Specifi cation, Revision 1.1, Section 2.1 for Timing Diagrams)
tHIGH SCL Serial Clock High Period IPULL-UP = 350μA, CLOAD = 250pF, RPU = 9.31k, l 4 μs VDD = 3V and VDD = 5.5V tLOW SCL Serial Clock Low Period IPULL-UP = 350μA, CLOAD = 250pF, RPU = 9.31k, l 4.7 15000 μs VDD = 3V and VDD = 5.5V tR SDA/SCL Rise Time CLOAD = 250pF, RPU = 9.31k, VDD = 3V l 1000 ns and VDD = 5.5V tF SDA/SCL Fall Time CLOAD = 250pF, RPU = 9.31k, VDD = 3V l 300 ns and VDD = 5.5V tSU:STA Start Condition Setup Time VDD = 3V and VDD = 5.5V l 4.7 μs tHD:STA Start Condition Hold Time VDD = 3V and VDD = 5.5V l 4 μs tHD:DAT SDA to SCL Falling-Edge Hold Time, VDD = 3V and VDD = 5.5V l 300 ns Slave Clocking in Data tTIMEOUT Time Between Receiving Valid VDD = 3V and VDD = 5.5V l 140 175 210 sec ChargingCurrent() and ChargingVoltage() Commands
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings temperature range are assured by design, characterization and correlation may cause permanent damage to the device. Exposure to any Absolute with statistical process controls. Maximum Rating condition for extended periods may affect device
Note 5:
Current accuracy dependent upon circuit compensation and sense reliability and lifetime. resistor.
Note 2:
See Test Circuit.
Note 6:
CTH is defi ned as the sum of capacitance on THA, THB and
Note 3:
Does not include tolerance of current sense resistor. SafetySignal.
Note 4:
The LTC4101E is guaranteed to meet performance specifi cations
Note 7:
The corresponding overrange bit will be set when a HEX value from 0°C to 85°C. Specifi cations over the –40°C to 85°C operating greater than or equal to this value is used. 4101fa 5
ELECTRICAL CHARACTERISTICS The
l
denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. VDCIN = 20V, VDD = 3.3V, VBAT = 4V unless otherwise noted. (Note 4) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Logic Levels
VIL SCL/SDA Input Low Voltage VDD = 3V and VDD = 5.5V l 0.8 V VIH SCL/SDA Input High Voltage VDD = 3V and VDD = 5.5V l 2.1 V VOL SDA Output Low Voltage IPULL-UP = 350μA l 0.4 V IIL SCL/SDA Input Current VSDA, VSCL = VIL –1 1 μA IIH SCL/SDA Input Current VSDA, VSCL = VIH –1 1 μA VOL SMBALERT Output Low Voltage IPULL-UP = 500μA l 0.4 V SMBALERT Output Pull-Up Current VSMBALERT = VOL –17.5 –10 –3.5 μA ILEAK SDA/SCL/SMBALERT Power Down Leakage VSDA, VSCL, VSMBALERT = 5.5V, VDD = OV l –2 2 μA VOL CHGEN Output Low Voltage IOL = 100μA l 0.5 V CHGEN Output Pull-Up Current VCHGEN = VOL –17.5 –10 –3.5 μA VIL CHGEN Input Low Voltage l 0.9 V VIH CHGEN Input High Voltage VDD = 3V l 2.5 V VDD = 5.5V 3.9 V Power-On Reset Duration VDD Ramp from 0V to >3V in <5μs 100 μs
SMBus Timing (Refer to System Management Bus Specifi cation, Revision 1.1, Section 2.1 for Timing Diagrams)
tHIGH SCL Serial Clock High Period IPULL-UP = 350μA, CLOAD = 250pF, RPU = 9.31k, l 4 μs VDD = 3V and VDD = 5.5V tLOW SCL Serial Clock Low Period IPULL-UP = 350μA, CLOAD = 250pF, RPU = 9.31k, l 4.7 15000 μs VDD = 3V and VDD = 5.5V tR SDA/SCL Rise Time CLOAD = 250pF, RPU = 9.31k, VDD = 3V l 1000 ns and VDD = 5.5V tF SDA/SCL Fall Time CLOAD = 250pF, RPU = 9.31k, VDD = 3V l 300 ns and VDD = 5.5V tSU:STA Start Condition Setup Time VDD = 3V and VDD = 5.5V l 4.7 μs tHD:STA Start Condition Hold Time VDD = 3V and VDD = 5.5V l 4 μs tHD:DAT SDA to SCL Falling-Edge Hold Time, VDD = 3V and VDD = 5.5V l 300 ns Slave Clocking in Data tTIMEOUT Time Between Receiving Valid VDD = 3V and VDD = 5.5V l 140 175 210 sec ChargingCurrent() and ChargingVoltage() Commands
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings temperature range are assured by design, characterization and correlation may cause permanent damage to the device. Exposure to any Absolute with statistical process controls. Maximum Rating condition for extended periods may affect device
Note 5:
Current accuracy dependent upon circuit compensation and sense reliability and lifetime. resistor.
Note 2:
See Test Circuit.
Note 6:
CTH is defi ned as the sum of capacitance on THA, THB and
Note 3:
Does not include tolerance of current sense resistor. SafetySignal.
Note 4:
The LTC4101E is guaranteed to meet performance specifi cations
Note 7:
The corresponding overrange bit will be set when a HEX value from 0°C to 85°C. Specifi cations over the –40°C to 85°C operating greater than or equal to this value is used. 4101fa 5