Datasheet LTC4100 (Analog Devices) - 5

制造商Analog Devices
描述Smart Battery Charger Controller
页数 / 页30 / 5 — e lecTrical characTerisTics The. denotes the specifications which apply …
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e lecTrical characTerisTics The. denotes the specifications which apply over the full operating

e lecTrical characTerisTics The denotes the specifications which apply over the full operating

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LTC4100
e lecTrical characTerisTics The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VDCIN = 20V, VDD = 3.3V, VBAT = 12V unless otherwise noted. (Note 4) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Logic Levels
VIL SCL/SDA Input Low Voltage VDD = 3V and VDD = 5.5V ● 0.8 V VIH SCL/SDA Input High Voltage VDD = 3V and VDD = 5.5V ● 2.1 V VOL SDA Output Low Voltage IPULL-UP = 350µA ● 0.4 V IIL SCL/SDA Input Current VSDA, VSCL = VIL –1 1 µA IIH SCL/SDA Input Current VSDA, VSCL = VIH –1 1 µA VOL SMBALERT Output Low Voltage IPULL-UP = 500µA ● 0.4 V SMBALERT Output Pull-Up Current VSMBALERT = VOL –17.5 –10 –3.5 µA ILEAK SDA/SCL/SMBALERT Power Down Leakage VSDA, VSCL, VSMBALERT = 5.5V, VDD = OV ● –2 2 µA VOL CHGEN Output Low Voltage IOL = 100µA ● 0.5 V CHGEN Output Pull-Up Current VCHGEN = VOL –17.5 –10 –3.5 µA VIL CHGEN Input Low Voltage ● 0.9 V VIH CHGEN Input High Voltage VDD = 3V ● 2.5 V VDD = 5.5V 3.9 V Power-On Reset Duration VDD Ramp from 0V to >3V in <5µs 100 µs
SMBus Timing (Refer to System Management Bus Specification, Revision 1.1, Section 2.1 for Timing Diagrams)
tHIGH SCL Serial Clock High Period IPULL-UP = 350µA, CLOAD = 250pF, ● 4 µs RPU = 9.31k, VDD = 3V and VDD = 5.5V tLOW SCL Serial Clock Low Period IPULL-UP = 350µA, CLOAD = 250pF, ● 4.7 15000 µs RPU = 9.31k, VDD = 3V and VDD = 5.5V tR SDA/SCL Rise Time CLOAD = 250pF, RPU = 9.31k, VDD = 3V and ● 1000 ns VDD = 5.5V tF SDA/SCL Fall Time CLOAD = 250pF, RPU = 9.31k, VDD = 3V and ● 300 ns VDD = 5.5V tSU:STA Start Condition Setup Time VDD = 3V and VDD = 5.5V ● 4.7 µs tHD:STA Start Condition Hold Time VDD = 3V and VDD = 5.5V ● 4 µs tHD:DAT SDA to SCL Falling-Edge Hold Time, Slave VDD = 3V and VDD = 5.5V ● 300 ns Clocking in Data tTIMEOUT Time Between Receiving Valid ChargingCurrent() VDD = 3V and VDD = 5.5V ● 140 175 210 sec and ChargingVoltage() Commands
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings
Note 5:
Current accuracy dependent upon circuit compensation and sense may cause permanent damage to the device. Exposure to any Absolute resistor. Maximum Rating condition for extended periods may affect device
Note 6:
CTH is defined as the sum of capacitance on THA, THB and reliability and lifetime. SafetySignal.
Note 2:
See Test Circuit.
Note 7:
The corresponding overrange bit will be set when a HEX value
Note 3:
Does not include tolerance of current sense resistor. greater than or equal to this value is used.
Note 4:
The LTC4100E is guaranteed to meet performance specifications from 0°C to 70°C. Specifications over the –40°C to 85°C operating temperature range are assured by design, characterization and correlation with statistical process controls. 4100fc For more information www.linear.com/LTC4100 5