Datasheet LT1505 (Analog Devices) - 6
| 制造商 | Analog Devices |
| 描述 | Constant-Current/Voltage High Efficiency Battery Charger |
| 页数 / 页 | 16 / 6 — PIN FUNCTIONS. BOOST (Pin 1):. INFET (Pin 8):. TGATE (Pin 2):. SW (Pin … |
| 文件格式/大小 | PDF / 170 Kb |
| 文件语言 | 英语 |
PIN FUNCTIONS. BOOST (Pin 1):. INFET (Pin 8):. TGATE (Pin 2):. SW (Pin 3):. CLP (Pin 9):. CLN (Pin 10):. SYNC (Pin 4):. COMP1 (Pin 11):
该数据表的模型线
文件文字版本
LT1505
U U U PIN FUNCTIONS BOOST (Pin 1):
This pin is used to bootstrap and supply to VIN with no resistor divider, the built-in 6.7V undervoltage power for the topside power switch gate drive and control lockout will be effective. Maximum voltage allowed on this circuity. In normal operation, VBOOST is powered from an pin is VCC. internally generated 8.6V regulator VGBIAS, VBOOST ≈ VCC
INFET (Pin 8):
For very low dropout applications, an + 9.1V when TGATE is high. Do not force an external external P-channel MOSFET can be used to connect the voltage on BOOST pin. input supply to VCC. This pin provides the gate drive for the
TGATE (Pin 2):
This pin provides gate drive to the topside PFET. The gate drive is clamped to 8V below VCC. The gate power FET. When TGATE is driven on, the gate voltage will is driven on (low) when VCC > (VBAT + 0.2V) and be approximately equal to VSW + 6.6V. A series resistor of VUV > 6.7V. The gate is off (high) when VCC < (VBAT + 0.2V). 5Ω to 10Ω should be used from this pin to the gate of the The body diode of the PFET is used to pull up VCC to turn topside FET. on the LT1505.
SW (Pin 3):
This pin is the reference point for the floating
CLP (Pin 9):
LT1505: Positive Input to the Input Current topside gate drive circuitry. It is the common connection Limit Amplifier CL1. The threshold is set at 92mV. When for the top and bottom side switches and the output used to limit input current, a filter is needed to filter out the inductor. This pin switches between ground and VCC with 200kHz switching noise. (LT1505-1: No Connection.) very high dv/dt rates. Care needs to be taken in the PC
CLN (Pin 10):
LT1505: Negative Input to the Input Current layout to keep this node from coupling to other sensitive Limit Amplifier CL1. When used, both CLP and CLN should nodes. A 1A Schottky clamp diode should be placed from be connected to a voltage higher than 6V and normally this pin to the ground pin, using very short traces to V prevent the chip substrate diode from turning on. See CC (to the VCC bypass capacitor for less noise). Maximum voltage allowed on both CLP and CLN is V Applications Information for more details. CC + 1V. (LT1505-1: No Connection.)
SYNC (Pin 4):
Synchronization Input. The LT1505 can be
COMP1 (Pin 11):
LT1505: Compensation Node for the synchronized to an external clock with pulses that have Input Current Limit Amplifier CL1. At input adapter current duty cycles between 10% and 95%. An internal one shot limit, this pin rises to 1V. By forcing COMP1 low with an that is triggered on the rising edge of the sync pulse makes external transistor, amplifier CL1 will be disabled (no this input insensitive to the duty cycle of the sync pulse. adapter current limit). Output current is less than 0.2mA. The input voltage range on this pin is 0V to 20V. This pin See the Figure 1 circuit for the required resistor and can float if not used. capacitor values. (LT1505-1: connect to GND.)
SHDN (Pin 5):
Shutdown. When this pin is pulled below 1V,
CAP (Pin 12):
A 0.1µF capacitor from CAP to ground is switching will stop, GBIAS will go low and the input cur- needed to filter the sampled charging current signal. This rents of CA1 will be off. Note that input current of about 4µA filtered signal is used to set the FLAG pin when the keeps the device in shutdown unless an external pull-up charging current drops below 20% of the programmed signal is applied. The voltage range on this pin is 0V to VCC. maximum charging current.
AGND (Pin 6):
Low Current Analog Ground.
FLAG (Pin 13):
This pin is an open-collector output that is
UV (Pin 7):
Undervoltage Lockout Input. The rising thresh- used to indicate the end of charge. The FLAG pin is driven old is 6.7V with a hysteresis of 0.5V. Switching stops in low when the charge current drops below 20% of the undervoltage lockout. When the input supply (normally programmed charge current. A pull-up resistor is the wall adapter output) to the chip is removed, the UV pin required if this function is used. This pin is capable of must be pulled down to below 0.7V (a 5k resistor from sinking at least 1mA. Maximum voltage on this pin is VCC. adapter output to GND is required), otherwise the reverse-
4.1V (Pin 14), 4.2V (Pin 15), 3CELL (Pin 16), V
battery current will be approximately 200µA instead of
FB (Pin 17):
These four pins are used to select the battery voltage 10µA. Do not leave the UV pin floating. If it is connected using the preset internal resistor network. The VFB pin is 1505fc 6
U U U PIN FUNCTIONS BOOST (Pin 1):
This pin is used to bootstrap and supply to VIN with no resistor divider, the built-in 6.7V undervoltage power for the topside power switch gate drive and control lockout will be effective. Maximum voltage allowed on this circuity. In normal operation, VBOOST is powered from an pin is VCC. internally generated 8.6V regulator VGBIAS, VBOOST ≈ VCC
INFET (Pin 8):
For very low dropout applications, an + 9.1V when TGATE is high. Do not force an external external P-channel MOSFET can be used to connect the voltage on BOOST pin. input supply to VCC. This pin provides the gate drive for the
TGATE (Pin 2):
This pin provides gate drive to the topside PFET. The gate drive is clamped to 8V below VCC. The gate power FET. When TGATE is driven on, the gate voltage will is driven on (low) when VCC > (VBAT + 0.2V) and be approximately equal to VSW + 6.6V. A series resistor of VUV > 6.7V. The gate is off (high) when VCC < (VBAT + 0.2V). 5Ω to 10Ω should be used from this pin to the gate of the The body diode of the PFET is used to pull up VCC to turn topside FET. on the LT1505.
SW (Pin 3):
This pin is the reference point for the floating
CLP (Pin 9):
LT1505: Positive Input to the Input Current topside gate drive circuitry. It is the common connection Limit Amplifier CL1. The threshold is set at 92mV. When for the top and bottom side switches and the output used to limit input current, a filter is needed to filter out the inductor. This pin switches between ground and VCC with 200kHz switching noise. (LT1505-1: No Connection.) very high dv/dt rates. Care needs to be taken in the PC
CLN (Pin 10):
LT1505: Negative Input to the Input Current layout to keep this node from coupling to other sensitive Limit Amplifier CL1. When used, both CLP and CLN should nodes. A 1A Schottky clamp diode should be placed from be connected to a voltage higher than 6V and normally this pin to the ground pin, using very short traces to V prevent the chip substrate diode from turning on. See CC (to the VCC bypass capacitor for less noise). Maximum voltage allowed on both CLP and CLN is V Applications Information for more details. CC + 1V. (LT1505-1: No Connection.)
SYNC (Pin 4):
Synchronization Input. The LT1505 can be
COMP1 (Pin 11):
LT1505: Compensation Node for the synchronized to an external clock with pulses that have Input Current Limit Amplifier CL1. At input adapter current duty cycles between 10% and 95%. An internal one shot limit, this pin rises to 1V. By forcing COMP1 low with an that is triggered on the rising edge of the sync pulse makes external transistor, amplifier CL1 will be disabled (no this input insensitive to the duty cycle of the sync pulse. adapter current limit). Output current is less than 0.2mA. The input voltage range on this pin is 0V to 20V. This pin See the Figure 1 circuit for the required resistor and can float if not used. capacitor values. (LT1505-1: connect to GND.)
SHDN (Pin 5):
Shutdown. When this pin is pulled below 1V,
CAP (Pin 12):
A 0.1µF capacitor from CAP to ground is switching will stop, GBIAS will go low and the input cur- needed to filter the sampled charging current signal. This rents of CA1 will be off. Note that input current of about 4µA filtered signal is used to set the FLAG pin when the keeps the device in shutdown unless an external pull-up charging current drops below 20% of the programmed signal is applied. The voltage range on this pin is 0V to VCC. maximum charging current.
AGND (Pin 6):
Low Current Analog Ground.
FLAG (Pin 13):
This pin is an open-collector output that is
UV (Pin 7):
Undervoltage Lockout Input. The rising thresh- used to indicate the end of charge. The FLAG pin is driven old is 6.7V with a hysteresis of 0.5V. Switching stops in low when the charge current drops below 20% of the undervoltage lockout. When the input supply (normally programmed charge current. A pull-up resistor is the wall adapter output) to the chip is removed, the UV pin required if this function is used. This pin is capable of must be pulled down to below 0.7V (a 5k resistor from sinking at least 1mA. Maximum voltage on this pin is VCC. adapter output to GND is required), otherwise the reverse-
4.1V (Pin 14), 4.2V (Pin 15), 3CELL (Pin 16), V
battery current will be approximately 200µA instead of
FB (Pin 17):
These four pins are used to select the battery voltage 10µA. Do not leave the UV pin floating. If it is connected using the preset internal resistor network. The VFB pin is 1505fc 6