Datasheet ADE9153A (Analog Devices) - 9

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Data Sheet ADE9153A PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 2 /CF X X ADY /T /R T K E L SO SI S Q 1 /DRE X SS SC MI MO RE IR CF Z 32 31 30 29 28 27 26 25 DGND 1 24 VDD DVDDOUT 2 23 FA0 CLKOUT 3 22 FA1 ADE9153A CLKIN 4 21 MSH TOP VIEW VDD 5 20 DGND (Not to Scale) IAMS 6 19 IBMS IAN 7 18 REFIN IAP 8 17 AGND 9 10 11 12 13 14 15 16 5 N P S P N T ND 2P IB IB M U VA VA AG UT VA DDO V DDO A V
03 0
NOTES
9-
1. EXPOSED PAD. THE EXPOSED PAD MUST BE LEFT FLOATING.
51 16 Figure 3. Pin Configuration
Table 6. Pin Function Descriptions Pin No. Mnemonic Description
1, 20 DGND Digital Ground. These pins provide the ground reference for the digital circuitry in the ADE9153A and form the return path for the Current Channel A and Current Channel B mSure currents. 2 DVDDOUT 1.7 V Output of the Digital LDO Regulator. Decouple this pin with a 0.1 μF ceramic capacitor in parallel with a 4.7 μF ceramic capacitor to Pin 1 (DGND). Do not connect external load circuitry to this pin. 3 CLKOUT Clock Output. Connect a crystal across CLKIN and CLKOUT to provide a clock source. An external buffer is required to drive other circuits from CLKOUT. 4 CLKIN Master Clock Input. Connect a crystal across CLKIN and CLKOUT to provide a clock source. See the ADE9153A Technical Reference Manual for details on choosing a suitable crystal. Alternatively, an external clock can be provided at the logic input. 5, 24 VDD Supply Voltage. These pins provide the supply voltage for the ADE9153A. Maintain the supply voltage at 3.3 V ± 10% for specified operation. Decouple these pins to AGND or DGND with a 4.7 μF capacitor in parallel with a ceramic 0.1 μF capacitor. 6 IAMS Output for the mSure Current Driver on Current Channel A (Phase Current Channel). IAMS is connected to the positive end of the shunt on the phase (to the side of the shunt closest to the load, on the same side as IAP). 7, 8 IAN, IAP Analog Inputs for Current Channel A (Phase Current Channel). The IAP and IAN current channel is ideal for use with shunts. The IAP (positive) and IAN (negative) inputs are fully differential voltage inputs with a maximum differential level of ±125 mV. These channels have an internal PGA gain of 16, 24, 32, and 38.4. Use these pins with the related input circuitry, as shown in Figure 37. 9, 17 AGND Ground Reference for the Analog Circuitry. See Figure 37 for information on how to connect these ground pins. 10 VDDOUT2P5 2.5 V Output of the Analog LDO Regulator. Decouple this pin with a 0.1 μF ceramic capacitor in parallel with a 4.7 μF ceramic capacitor to Pin 9 (AGND). Do not connect external load circuitry to this pin. 11, 12 IBN, IBP Analog Inputs for Current Channel B (Neutral Current Channel). The IBP and IBN current channel is ideal for use with CTs. The IBP (positive) and IBN (negative) inputs are fully differential voltage inputs with a maximum differential level of ±1000 mV. These channels have an internal PGA gain of 1, 2, or 4. Use these pins with the related input circuitry, as shown in Figure 37. 13 VAMS Path for mSure on the Voltage Channel. VAMS is connected to the bottom end of the resistor divider, which is typically connected to the phase, as shown in Figure 1. 14, 15 VAP, VAN Analog Inputs for the Voltage Channels. The VAP (positive) and VAN (negative) inputs are fully differential with an input level of 0.1 V to 1.7 V. Use these pins with the related input circuitry, as shown in Figure 37. 16 AVDDOUT 1.9 V Output of the Analog LDO Regulator. Decouple this pin with a 0.1 μF ceramic capacitor in parallel with a 4.7 μF ceramic capacitor to Pin 17 (AGND). Do not connect external load circuitry to this pin. Rev. 0 | Page 9 of 50 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION TYPICAL APPLICATIONS CIRCUIT TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS AUTOCALIBRATION SPI TIMING CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS ENERGY LINEARITY OVER SUPPLY AND TEMPERATURE ENERGY ERROR OVER FREQUENCY AND POWER FACTOR RMS LINEARITY OVER TEMPERATURE AND RMS ERROR OVER FREQUENCY SIGNAL-TO-NOISE RATIO (SNR) PERFORMANCE OVER DYNAMIC RANGE TEST CIRCUIT TERMINOLOGY THEORY OF OPERATION mSURE AUTOCALIBRATION FEATURE mSure System Warning Interrupts MEASUREMENTS Current Channel Current Channel Gain, xIGAIN High-Pass Filter Digital Integrator Phase Compensation Voltage Channel RMS and Power Measurements Total RMS Total Active Power Fundamental Reactive Power Total Apparent Power Energy Accumulation, Power Accumulation, and No Load Detection Features Energy Accumulation Energy Accumulation Modes Reset Energy Register on Read Power Accumulation No Load Detection Feature Digital to Frequency Conversion—CFx Output Calibration Frequency (CF) Energy Selection Configuring the CFx Pulse Width CFx Pulse Sign Clearing the CFx Accumulator POWER QUALITY MEASUREMENTS Zero-Crossing Detection CF1/ZX/DREADY Zero-Crossing Timeout Line Period Calculation Angle Measurement One Cycle RMS Measurement Dip and Swell Indication Overcurrent Indication Peak Detection Power Factor Temperature APPLICATIONS INFORMATION INTERRUPTS/EVENTS PIN INTERRUPTS SERVICING INTERRUPTS CF2/ZX/DREADY EVENT PIN ACCESSING ON-CHIP DATA SPI PROTOCOL OVERVIEW UART INTERFACE COMMUNICATION VERIFICATION REGISTERS CRC OF CONFIGURATION REGISTERS CONFIGURATION LOCK REGISTER INFORMATION REGISTER SUMMARY REGISTER DETAILS OUTLINE DIMENSIONS ORDERING GUIDE