Datasheet ADE9000 (Analog Devices) - 6

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ADE9000 Data Sheet Parameter Min Typ Max Unit Test Conditions/Comments
ADC PGA Gain Settings (PGA_GAIN) 1, 2, or 4 V/V PGA gain setting is referred to as PGA_GAIN Differential Input Voltage Range −1/Gain +1/Gain V 707 mV rms, when VREF = 1.25 V, this voltage (VxP to VxN, IxP to IxN) corresponds to 53 million codes Maximum Operating Voltage on Analog −0.6 +0.6 V Voltage on the pin with respect to ground Input Pins (VxP, VxN, IxP, and IxN) (GND = AGND = DGND = REFGND) Signal-to-Noise Ratio (SNR)2 PGA = 1 96 dB 32 kSPS, sinc4 output, VIN = −0.5 dB from FS 101 dB 8 kSPS, sinc4 + infinite impulse response (IIR), low-pass filter (LPF) output, VIN = −0.5 dB from FS PGA = 4 93 dB 32 kSPS, sinc4 output 96 dB 8 kSPS, sinc4 + IIR LPF output Total Harmonic Distortion (THD)2 PGA = 1 −101 −95 dB 32 kSPS, sinc4 output, VIN = −0.5 dB from FS −101 −95 dB 8 kSPS, sinc4 + IIR LPF output, VIN = −0.5 dB from FS PGA = 4 −107 −99 dB 32 kSPS, sinc4 output −107 −99 dB 8 kSPS, sinc4 + IIR LPF output Signal-to-Noise and Distortion Ratio (SINAD)2 PGA = 1 95 dB 32 kSPS, sinc4 output, VIN = −0.5 dB from FS 98 dB 8 kSPS, sinc4 + IIR LPF output, VIN = −0.5 dB from FS PGA = 4 93 dB 32 kSPS, sinc4 output 96 dB 8 kSPS, sinc4 + IIR LPF output Spurious-Free Dynamic Range (SFDR)2 PGA = 1 100 dB 32 kSPS, sinc4 output, VIN = −0.5 dB from FS 100 dB 8 kSPS, sinc4 + IIR LPF output, VIN = −0.5 dB from FS Output Pass Band (0.1dB) Sinc4 Outputs 1.344 kHz 32 kSPS, sinc4 output Sinc4 + IIR LPF Outputs 1.344 kHz 8 kSPS output Output Bandwidth (−3 dB) 2 Sinc4 Outputs 7.2 kHz 32 kSPS, sinc4 output Sinc4 + IIR LPF Outputs 3.2 kHz 8 kSPS output Crosstalk2 −120 dB At 50 Hz or 60 Hz, see the Terminology section AC Power Supply Rejection Ratio −120 dB At 50 Hz, see the Terminology section (AC PSRR)2 Common-Mode Rejection Ratio 115 dB At 100 Hz and 120 Hz (AC CMRR)2 Gain Error ±0.3 ±1 %typ See the Terminology section Gain Drift2 ±3 ppm/°C See the Terminology section Offset ±0.040 ±3.8 mV See the Terminology section Offset Drift2 0 ±2 µV/°C See the Terminology section Channel Drift (PGA, ADC, Internal ±7 ±25 ppm/°C PGA = 1, internal VREF Voltage Reference) ±7 ±25 ppm/°C PGA = 2, internal VREF ±7 ±25 ppm/°C PGA = 4, internal VREF Differential Input Impedance (DC) 165 185 kΩ PGA = 1, see the Terminology section 80 90 kΩ PGA = 2 40 45 kΩ PGA = 4 Rev. A | Page 6 of 72 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION REVISION HISTORY TYPICAL APPLICATIONS CIRCUIT SPECIFICATIONS TIMING CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS ENERGY LINEARITY OVER SUPPLY AND TEMPERATURE ENERGY ERROR OVER FREQUENCY AND POWER FACTOR ENERGY LINEARITY REPEATABILITY RMS LINEARITY OVER TEMPERATURE AND RMS ERROR OVER FREQUENCY ENERGY AND RMS LINEARITY WITH INTEGRATOR ON ENERGY AND RMS ERROR OVER FREQUENCY WITH INTEGRATOR ON SIGNAL-TO-NOISE RATIO PERFORMANCE TEST CIRCUIT TERMINOLOGY THEORY OF OPERATION MEASUREMENTS Current Channel ADC_REDIRECT Multiplexer Current Channel Gain, xIGAIN IB Calculation Using ICONSEL High-Pass Filter Digital Integrator Phase Compensation Multipoint Phase and Gain Calibration Voltage Channel RMS and Power Measurements Total and Fundamental RMS Total and Fundamental Active Power Total and Fundamental Reactive Power Total and Fundamental Apparent Power No Load Detection, Energy Accumulation, and Power Accumulation Features No Load Detection Feature Energy Accumulation Power Accumulation Digital to Frequency Conversion—CFx Output Energy and Phase Selection Configuring the CFx Pulse Width CFx Pulse Sign Clearing the CFx Accumulator POWER QUALITY MEASUREMENTS Zero-Crossing Detection CF3/ZX Zero-Crossing Timeout Line Period Calculation Angle Measurement Phase Sequence Error Detection Fast RMS½ Measurement 10 Cycle RMS/12 Cycle RMS Dip and Swell Indication Overcurrent Indication Peak Detection Power Factor Total Harmonic Distortion (THD) Resampling 128 Points per Cycle Temperature WAVEFORM BUFFER INTERRUPTS/EVENTS ACCESSING ON-CHIP DATA SPI PROTOCOL OVERVIEW ADDITIONAL COMMUNICATION VERIFICATION REGISTERS CRC OF CONFIGURATION REGISTERS CONFIGURATION LOCK REGISTER MAP REGISTER DETAILS OUTLINE DIMENSIONS ORDERING GUIDE