Datasheet ADE9078 (Analog Devices) - 7

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Data Sheet ADE9078 Parameter Min Typ Max Unit Test Conditions/Comments
LOGIC OUTPUTS MISO, IRQ0, and IRQ1 VDD = 2.7 V Output Voltage High, VOH   2.4 V ISOURCE = 1 mA Low, VOL 0.8 V ISINK = 4 mA CF1, CF2, CF3, and CF4 VDD = 2.7 V Output Voltage High, VOH 2.4 V ISOURCE = 3 mA Low, VOL 0.8 V ISINK = 8 mA LOW DROPOUT REGULATORS (LDOs) AVDD 1.9 V See the Power-On Sequence section DVDD 1.7 V POWER SUPPLY   For specified performance VDD 2.7 3.3 3.63 V Supply Current (VDD) VDD = 3.63 V Power Save Mode 0 (PSM0)  10 12 mA Normal mode, seven ADCs enabled 9.5 11 mA Normal mode, seven ADCs enabled, total reactive power computation disabled 10.5 12 mA Normal mode, seven ADCs enabled, waveform buffer enabled 10 11.6 mA Normal mode, six ADCs enabled Power Save Mode 1 (PSM1) 9 10.6 mA Fast rms, active power, and total reactive power measurement within 30 ms for tamper detection Power Save Mode 2 (PSM2) 115 200 μA Compares current to threshold, AVDD = 0 V, DVDD = 0 V Power Save Mode 3 (PSM3) 50 200 nA Idle, AVDD = 0 V, DVDD = 0 V 1 Throughout this data sheet, multifunction pins, such as CF3/ZX, are referred to either by the entire pin name or by a single function of the pin, for example, CF3, when only that function is relevant. 2 Tested during device characterization.
TIMING CHARACTERISTICS Table 2. Parameter Symbol Min Typ Max Unit
SS to SCLK Edge tSS 10 ns SCLK Frequency 10 MHz SCLK Low Pulse Width tSL 40 ns SCLK High Pulse Width tSH 40 ns Data Output Valid After SCLK Edge tDAV 40 ns Data Input Setup Time Before SCLK Edge tDSU 10 ns Data Input Hold Time After SCLK Edge tDHD 10 ns Data Output Fall Time tDF 10 ns Data Output Rise Time tDR 10 ns SCLK Fall Time tSF 10 ns SCLK Rise Time tSR 10 ns MISO Disable After SS Rising Edge tDIS 100 ns SS High After SCLK Edge tSFS 0 ns Rev. 0 | Page 7 of 107 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TOTAL ENERGY LINEARITY OVER SUPPLY AND TEMPERATURE FUNDAMENTAL ENERGY LINEARITY WITH FIFTH HARMONIC OVER SUPPLY AND TEMPERATURE TOTAL ENERGY ERROR OVER FREQUENCY RMS LINEARITY OVER TEMPERATURE AND RMS ERROR OVER FREQUENCY ENERGY LINEARITY REPEATABILITY TOTAL ENERGY AND RMS LINEARITY WITH INTEGRATOR ON TOTAL ENERGY ERROR OVER FREQUENCY WITH INTEGRATOR ON TEST CIRCUIT TERMINOLOGY THEORY OF OPERATION ADC Overview Analog Input Configuration Fully Differential Inputs Interfacing to Current and Voltage Sensors Internal RF Immunity Filter Modes of Operation Output Data Rates and Format Voltage Reference CRYSTAL OSCILLATOR/EXTERNAL CLOCK Crystal Selection Load Capacitor Calculation Load Capacitor Calculation Example POWER MANAGEMENT Power Modes Power-On Sequence Brownout Detection Reset Changing to PSM2 or PSM3 MEASUREMENTS (NORMAL MODE) Current Channel Current Channel Measurement Update Rates ADC_REDIRECT Multiplexer Current Channel Gain, xIGAIN IB Calculation Using ICONSEL High-Pass Filter Digital Integrator Phase Compensation Multipoint Gain and Phase Calibration Multipoint Gain and Phase Single-Point Gain and Phase Voltage Channel Voltage Channel Measurements Voltage Channel Gain Energy Measurements Overview Per Phase Energy Measurements Update Rate Power-Based and Filter-Based RMS Measurement Algorithms Filter-Based Total RMS Neutral Current RMS, RMS of Sum of Instantaneous Currents Total Active Power Total Reactive Power Total Apparent Power Fundamental Reactive Power Power Factor Energy Accumulation Signed Energy Accumulation Modes Total Active Energy Accumulation Modes Reactive Energy Accumulation Modes No Load Detection No Load Indications Energy Accumulation Details Internal Energy Register Overflow Rate User Energy Register Update Rate, EGYRDY Reloading or Accumulating User Energy Register User Energy Register Overflow Rate Accessing the User Energy Registers Read User Energy Register with Reset User Energy Register Use Models Digital to Frequency Conversion—CFx Output Energy and Phase Selection Configuring the Maximum CF Pulse Output Frequency Configuring the CF Pulse Width CFx Pulse Sign Clearing the CFx Accumulator Disabling the CFx Pulse Output and CFx Interrupt MEASUREMENTS (PSM1) Overview IRMS, VRMS, and Active Power VAR PSM1 Startup Flow from PSM2 and PSM3 PSM1 Startup Flow from PSM0 Power Accumulation Power Accumulation Details Accessing the User Power Registers Power Sign Detection Zero-Crossing Detection Combined Voltage Zero Crossing Zero-Crossing Output Rates Zero-Crossing Timeout Line Period Calculation Angle Measurement Phase Sequence Error Detection 4-Wire Wye and 4-Wire Delta 3-Wire Delta Peak Detection MEASUREMENTS (PSM2) Overview Low Power Comparator KEY FEATURES FLEXIBLE WAVEFORM BUFFER WITH RESAMPLING MULTIPOINT PHASE/GAIN CALIBRATION RMS OF SUM OF INSTANTANEOUS CURRENTS MEASUREMENT TAMPER MODES POWER FACTOR ZERO-CROSSING TIMEOUT DETECTION LINE PERIOD MEASUREMENT ANGLE MEASUREMENT PHASE SEQUENCE ERROR DETECTION QUICK START APPLICATIONS INFORMATION NON-BLONDEL COMPLIANT METERS APPLYING THE ADE9078 TO A 4-WIRE WYE SERVICE APPLYING THE ADE9078 TO A 3-WIRE DELTA SERVICE APPLYING THE ADE9078 TO A NON-BLONDEL COMPLIANT, 4-WIRE WYE SERVICE APPLYING THE ADE9078 TO A NON-BLONDEL COMPLIANT, 4-WIRE DELTA SERVICE SERVICE TYPE SUMMARY ACCESSING ON-CHIP DATA SPI PROTOCOL OVERVIEW SPI WRITE SPI READ SPI BURST READ SPI PROTOCOL CRC CRC Algorithm ADDITIONAL COMMUNICATION VERIFICATION REGISTERS CRC OF CONFIGURATION REGISTERS CONFIGURATION LOCK WAVEFORM BUFFER FIXED DATA RATE WAVEFORMS Waveform Buffer Filling Indication—Fixed Data Rate Samples FIXED DATA RATE WAVEFORMS FILLING AND TRIGGER-BASED MODES Stop When Buffer Is Full Mode Continuous Fill Mode Stop Filling on Trigger Center Capture Around Trigger Save Event Address and Keep Filling RESAMPLED WAVEFORMS CONFIGURING THE WAVEFORM BUFFER BURST READ WAVEFORM BUFFER SAMPLES FROM SPI Example 1: Fixed Data Rate Data, Seven Channel Samples Example 2: Resampled Data, Phase C (I and V Samples) Example 3: Fixed Data Rate Data, Single Address Read Mode Example 4: Resampled Data, Single Address Read Mode SPI CRC when Reading the Waveform Buffer SPI Last Data Register when Reading the Waveform Buffer INTERRUPTS/EVENTS INTERRUPTS (IRQ0\ AND IRQ1\) EVENT\ STATUS BITS IN ADDITIONAL REGISTERS No Load TROUBLESHOOTING SPI DOES NOT WORK PSM2_CFG REGISTER VALUE IS NOT RETAINED WHEN GOING FROM PSM2 OR PSM3 TO PSM0 REGISTER INFORMATION REGISTER DETAILS OUTLINE DIMENSIONS ORDERING GUIDE