Datasheet ADE7880 (Analog Devices) - 7

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Data Sheet ADE7880 Parameter1, 2 Min Typ Max Unit Test Conditions/Comments
WAVEFORM SAMPLING Sampling CLKIN/2048, 16.384 MHz/2048 = 8 kSPS Current and Voltage Channels See the Waveform Sampling Mode section Signal-to-Noise Ratio, SNR 72 dB PGA = 1, fundamental frequency = 45 Hz to 65 Hz, see the Terminology section Signal-to-Noise-and-Distortion Ratio, 72 dB PGA = 1, fundamental frequency = 45 Hz SINAD to 65 Hz, see the Terminology section Bandwidth (−3 dB) 3.3 kHz TIME INTERVAL BETWEEN PHASES Measurement Error 0.3 Degrees Line frequency = 45 Hz to 65 Hz, HPF on CF1, CF2, CF3 PULSE OUTPUTS Maximum Output Frequency 68.818 kHz WTHR = VARTHR = VATHR = 3 Duty Cycle 50 % If CF1, CF2, or CF3 frequency > 6.25 Hz and CFDEN is even and > 1 (1 + 1/CFDEN) × % If CF1, CF2, or CF3 frequency > 6.25 Hz 50 and CFDEN is odd and > 1 Active Low Pulse Width 80 ms If CF1, CF2, or CF3 frequency < 6.25 Hz Jitter 0.04 % For CF1, CF2, or CF3 frequency = 1 Hz and nominal phase currents are larger than 10% of full scale REFERENCE INPUT REFIN/OUT Input Voltage Range 1.1 1.3 V Minimum = 1.2 V − 8%; maximum = 1.2 V + 8% Input Capacitance 10 pF ON-CHIP REFERENCE Nominal 1.2 V at the REFIN/OUT pin at TA = 25°C PSM0 and PSM1 Modes Temperature Coefficient −50 ±20 +50 ppm/°C Drift across the entire temperature range of −40°C to +85°C is calculated with reference to 25°C; see the Reference Circuit section for more details CLKIN See the Crystal Circuit section for more details Input Clock Frequency 16.22 16.384 16.55 MHz LOGIC INPUTS—MOSI/SDA, SCLK/SCL, SS, RESET, PM0, AND PM1 Input High Voltage, VINH 2.4 V VDD = 3.3 V Input Current, IIN 82 nA Input = VDD = 3.3 V Input Low Voltage, VINL 0.8 V VDD = 3.3 V Input Current, IIN −7.3 µA Input = 0, VDD = 3.3 V Input Capacitance, CIN 10 pF LOGIC OUTPUTS—IRQ0, IRQ1, AND VDD = 3.3 V MISO/HSD Output High Voltage, VOH 3.0 V ISOURCE = 800 µA Output Low Voltage, VOL 0.4 V ISINK = 2 mA CF1, CF2, CF3/HSCLK Output High Voltage, VOH 2.4 V ISOURCE = 500 µA Output Low Voltage, VOL 0.4 V ISINK = 8 mA POWER SUPPLY For specified performance PSM0 Mode VDD Pin 2.97 3.63 V Minimum = 3.3 V − 10%; maximum = 3.3 V + 10% IDD 25 28 mA Rev. C | Page 7 of 107 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS TIMING CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TEST CIRCUIT TERMINOLOGY POWER MANAGEMENT PSM0—NORMAL POWER MODE (ALL PARTS) PSM1—REDUCED POWER MODE PSM2—LOW POWER MODE PSM3—SLEEP MODE (ALL PARTS) POWER-UP PROCEDURE HARDWARE RESET SOFTWARE RESET FUNCTIONALITY THEORY OF OPERATION ANALOG INPUTS ANALOG-TO-DIGITAL CONVERSION Antialiasing Filter ADC Transfer Function CURRENT CHANNEL ADC Current Waveform Gain Registers Current Channel HPF Current Channel Sampling di/dt CURRENT SENSOR AND DIGITAL INTEGRATOR VOLTAGE CHANNEL ADC Voltage Waveform Gain Registers Voltage Channel HPF Voltage Channel Sampling CHANGING PHASE VOLTAGE DATA PATH POWER QUALITY MEASUREMENTS Zero-Crossing Detection Zero-Crossing Timeout Phase Sequence Detection Time Interval Between Phases Period Measurement Phase Voltage Sag Detection Sag Level Set Peak Detection Overvoltage and Overcurrent Detection Overvoltage and Overcurrent Level Set Neutral Current Mismatch PHASE COMPENSATION REFERENCE CIRCUIT DIGITAL SIGNAL PROCESSOR ROOT MEAN SQUARE MEASUREMENT Current RMS Calculation Current RMS Offset Compensation Current Mean Absolute Value Calculation Current MAV Gain and Offset Compensation Voltage Channel RMS Calculation Voltage RMS Offset Compensation Voltage RMS in 3-Phase, 3-Wire Delta Configurations ACTIVE POWER CALCULATION Total Active Power Calculation Fundamental Active Power Calculation Managing Change in Fundamental Line Frequency Active Power Gain Calibration Active Power Offset Calibration Sign of Active Power Calculation Active Energy Calculation Integration Time Under Steady Load Active Energy Accumulation Modes Line Cycle Active Energy Accumulation Mode FUNDAMENTAL REACTIVE POWER CALCULATION Fundamental Reactive Power Gain Calibration Fundamental Reactive Power Offset Calibration Sign of Fundamental Reactive Power Calculation Fundamental Reactive Energy Calculation Integration Time Under Steady Load Fundamental Reactive Energy Accumulation Modes Line Cycle Reactive Energy Accumulation Mode APPARENT POWER CALCULATION Apparent Power Gain Calibration Apparent Power Offset Calibration Apparent Power Calculation Using VNOM Apparent Energy Calculation Integration Time Under Steady Load Apparent Energy Accumulation Modes Line Cycle Apparent Energy Accumulation Mode POWER FACTOR CALCULATION HARMONICS CALCULATIONS Harmonics Calcuations Theory Configuring the Harmonic Calculations Harmonic Calculations When a Phase is Monitored Harmonic Calculations When the Neutral is Monitored Configuring Harmonic Calculations Update Rate Recommended Approach to Managing Harmonic Calculations WAVEFORM SAMPLING MODE ENERGY-TO-FREQUENCY CONVERSION Synchronizing Energy Registers with CFx Outputs Energy Registers and CF Outputs for Various Accumulation Modes Sign of Sum of Phase Powers in the CFx Data Path NO LOAD CONDITION No Load Detection Based On Total Active Power and Apparent Power No Load Detection Based on Fundamental Active and Reactive Powers No Load Detection Based on Apparent Power CHECKSUM REGISTER INTERRUPTS Using the Interrupts with an MCU SERIAL INTERFACES Serial Interface Choice Communication Verification I2C-Compatible Interface I2C Write Operation I2C Read Operation I2C Read Operation of Harmonic Calculations Registers SPI-Compatible Interface SPI Read Operation SPI Read Operation of Harmonic Calculations Registers SPI Write Operation HSDC Interface ADE7880 QUICK SETUP AS ENERGY METER LAYOUT GUIDELINES CRYSTAL CIRCUIT ADE7880 EVALUATION BOARD DIE VERSION SILICON ANOMALY ADE7880 FUNCTIONALITY ISSUES FUNCTIONALITY ISSUES SECTION 1. ADE7880 FUNCTIONALITY ISSUES REGISTERS LIST OUTLINE DIMENSIONS ORDERING GUIDE