Datasheet ADE7854, ADE7858, ADE7868, ADE7878 (Analog Devices) - 10

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ADE7854/ADE7858/ADE7868/ADE7878 Data Sheet Parameter1, 2 Min Typ Max Unit Test Conditions/Comments
MEAN ABSOLUTE VALUE (MAV) MEASUREMENT (ADE7868 AND ADE7878) I mav Measurement Bandwidth (PSM1 260 Hz Mode) I mav Measurement Error (PSM1 Mode) 0.5 % Over a dynamic range of 100 to 1, PGA = 1, 2, 4, 8 ANALOG INPUTS Maximum Signal Levels ±500 mV peak PGA = 1, differential inputs between the following pins: IAP and IAN, IBP and IBN, ICP and ICN; single-ended inputs between the following pins: VAP and VN, VBP and VN, VCP, and VN Input Impedance (DC) IAP, IAN, IBP, IBN, ICP, ICN, VAP, VBP, 400 kΩ and VCP Pins VN Pin 130 kΩ ADC Offset −24 mV PGA = 1, uncalibrated error, see the Terminology section Gain Error ±4 % External 1.2 V reference WAVEFORM SAMPLING Sampling CLKIN/2048, 16.384 MHz/2048 = 8 kSPS Current and Voltage Channels See the Waveform Sampling Mode section Signal-to-Noise Ratio, SNR 74 dB PGA = 1, fundamental frequency: 45 Hz to 65 Hz, see the Terminology section Signal-to-Noise-and-Distortion Ratio, 74 dB PGA = 1; fundamental frequency: 45 Hz to SINAD 65 Hz, see the Terminology section Bandwidth (−3 dB) 2 kHz TIME INTERVAL BETWEEN PHASES Measurement Error 0.3 Degrees Line frequency = 45 Hz to 65 Hz, HPF on CF1, CF2, CF3 PULSE OUTPUTS Maximum Output Frequency 8 kHz WTHR = VARTHR = VATHR = PMAX = 33,516,139 Duty Cycle 50 % If CF1, CF2, or CF3 frequency > 6.25 Hz and CFDEN is even and > 1 (1 + 1/CFDEN) If CF1, CF2, or CF3 frequency > 6.25 Hz and × 50% CFDEN is odd and > 1 Active Low Pulse Width 80 ms If CF1, CF2, or CF3 frequency < 6.25 Hz Jitter 0.04 % For CF1, CF2, or CF3 frequency = 1 Hz and nominal phase currents are larger than 10% of full scale REFERENCE INPUT REFIN/OUT Input Voltage Range 1.1 1.3 V Minimum = 1.2 V − 8%; maximum = 1.2 V + 8% Input Capacitance 10 pF ON-CHIP REFERENCE Nominal 1.2 V at the REFIN/OUT pin at TA = 25°C PSM0 and PSM1 Modes Temperature Coefficient −50 ±5 +50 ppm/°C Drift across the entire temperature range of −40°C to +85°C is calculated with reference to 25°C; see the Reference Circuit section for more details CLKIN All specifications CLKIN of 16.384 MHz. See the Crystal Circuit section for more details. Input Clock Frequency 16.22 16.384 16.55 MHz LOGIC INPUTS—MOSI/SDA, SCLK/SCL, SS, RESET, PM0, AND PM1 Input High Voltage, VINH 2.0 V VDD = 3.3 V ± 10% Input Low Voltage, VINL 0.8 V VDD = 3.3 V ± 10% Input Current, IIN −8.7 µA Input = 0 V, VDD = 3.3 V 3 μA Input = VDD = 3.3 V Input Capacitance, CIN 10 pF Rev. H | Page 10 of 100 Document Outline Features Applications General Description Table of Contents Revision History Functional Block Diagrams Specifications Timing Characteristics Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Test Circuit Terminology Power Management PSM0—Normal Power Mode (All Parts) PSM1—Reduced Power Mode (ADE7868, ADE7878 Only) PSM2—Low Power Mode (ADE7868, ADE7878 Only) PSM3—Sleep Mode (All Parts) Power-Up Procedure Hardcore Reset Software Reset Functionality Theory of Operation Analog Inputs Analog-to-Digital Conversion Antialiasing Filter ADC Transfer Function Current Channel ADC Current Waveform Gain Registers Current Channel HPF Current Channel Sampling di/dt Current Sensor and Digital Integrator Voltage Channel ADC Voltage Waveform Gain Registers Voltage Channel HPF Voltage Channel Sampling Changing Phase Voltage Datapath POWER QUALITY MEASUREMENTS Zero-Crossing Detection Zero-Crossing Timeout Phase Sequence Detection Time Interval Between Phases Period Measurement Phase Voltage Sag Detection SAG Level Set Peak Detection Overvoltage and Overcurrent Detection Overvoltage and Overcurrent Level Set Neutral Current Mismatch—ADE7868, ADE7878 Phase Compensation Reference Circuit Digital Signal Processor Root Mean Square Measurement Current RMS Calculation Current RMS Offset Compensation Current Mean Absolute Value Calculation—ADE7868 and ADE7878 Only Current MAV Gain and Offset Compensation Voltage Channel RMS Calculation Voltage RMS Offset Compensation Active Power Calculation Total Active Power Calculation Fundamental Active Power Calculation—ADE7878 Only Active Power Gain Calibration Active Power Offset Calibration Sign of Active Power Calculation Active Energy Calculation Integration Time Under Steady Load Energy Accumulation Modes Line Cycle Active Energy Accumulation Mode Reactive Power Calculation—ADE7858, ADE7868, ADE7878 Only Reactive Power Gain Calibration Reactive Power Offset Calibration Sign of Reactive Power Calculation Reactive Energy Calculation Integration Time Under A Steady Load Energy Accumulation Modes Line Cycle Reactive Energy Accumulation Mode Apparent Power Calculation Apparent Power Gain Calibration Apparent Power Offset Calibration Apparent Power Calculation Using VNOM Apparent Energy Calculation Integration Time Under Steady Load Energy Accumulation Mode Line Cycle Apparent Energy Accumulation Mode Waveform Sampling Mode Energy-to-Frequency Conversion Synchronizing Energy Registers with CFx Outputs CF Outputs for Various Accumulation Modes Sign of Sum-of-Phase Powers in the CFx Datapath No Load Condition No Load Detection Based On Total Active, Reactive Powers No Load Detection Based on Fundamental Active and Reactive Powers—ADE7878 Only No Load Detection Based on Apparent Power Checksum Register Interrupts Using the Interrupts with an MCU Serial Interfaces Serial Interface Choice I2C-Compatible Interface I2C Write Operation I2C Read Operation SPI-Compatible Interface SPI Read Operation SPI Write Operation HSDC Interface Quick Setup as Energy Meter Layout Guidelines Crystal Circuit ADE7878 Evaluation Board Die Version Silicon Anomaly ADE7854/ADE7858/ADE7868/ADE7878 Functionality Issues Functionality Issues SECTION 1. ADE7854/ADE7858/ADE7868/ADE7878 Functionality Issues Registers List Outline Dimensions Ordering Guide