Datasheet ADE7116, ADE7166, ADE7169, ADE7566, ADE7569 (Analog Devices)

Single-Phase Energy Measurement IC with 8052 MCU, RTC, and LCD Driver Data Sheet ADE7116/ ADE7166 /ADE7169/ ADE7566 /ADE7569 GENERAL FEATURES MICROPROCESSOR FEATURES Wide supply voltage operation: 2.4 V to 3.7 V 8052-based core Internal bipolar switch between regulated and battery inputs Single-cycle 4 MIPS 8052 core Ultralow power operation with power saving modes (PSM) 8052-compatible instruction set Full operation: 4 mA to 1.6 mA (PLL clock dependent) 32.768 kHz external crystal with on-chip PLL Battery mode: 3.2 mA to 400 µA (PLL clock dependent) 2 external interrupt sources Sleep mode External reset pin Real-time clock (RTC) mode: 1.5 µA Low power battery mode RTC and LCD mode: 38 µA (LCD charge pump enabled) Wake up from input/output (I/O), temperature change1, Reference: 1.2 V ± 0.1% (10 ppm/°C drift) alarm, and universal asynchronous receiver/transmitter 64-lead RoHS package option (UART) Low profile quad flat package (LQFP) LCD driver operation Operating temperature range: −40°C to +85°C Temperature measurement ENERGY MEASUREMENT FEATURES Real-time clock (RTC) Counter for seconds, minutes, and hours Proprietary analog-to-digital converters (ADCs) and digital Automatic battery switchover for RTC backup signal processing (DSP) provide high accuracy active Operation down to 2.4 V (watt), reactive (var), and apparent energy (volt ampere Ultralow battery supply current: 1.5 µA (VA)) measurement Selectable output frequency: 1 Hz to 16 kHz <0.1% error on active energy over a dynamic range of Embedded digital crystal frequency compensation for 1000 to 1 at 25°C calibration and temperature variation of 2 ppm resolution <0.5% error on reactive energy over a dynamic range of Integrated LCD driver 1000 to 1 at 25°C (ADE7169 a nd ADE7569 only) 108-segment driver for the ADE7566 /ADE7569 and <0.5% error on root mean square (rms) measurements 104-segment driver for the ADE7116/ ADE7166 /ADE7169 over a dynamic range of 500 to 1 for current (I ) and rms 2×, 3×, or 4× multiplexing 100 to 1 for voltage (V ) at 25°C rms LCD voltages generated internally1 or with external resistors Supports IEC 62053-21, IEC 62053-22, and IEC 62053-23; Internal adjustable drive voltages up to 5 V independent EN 50470-3 Class A, Class B, and Class C; and ANSI C12-16 of power supply level1 Differential input with programmable gain amplifiers (PGAs) On-chip peripherals supports shunts, current transformers, and di/dt current UART interface sensors (ADE7169 a nd ADE7569 only) SPI or I2C 2 current inputs for antitamper detection in the ADE7116/ Watchdog timer ADE7166 /ADE7169 Power supply management with user selectable levels High frequency outputs proportional to I , active, reactive, rms Memory: 16 kB flash memory, 512 bytes RAM or apparent power (AP) Development tools Table 1. Features Available on Each Device Single pin emulation IDE based assembly and C-source debugging Feature Part No.
Antitamper ADE7116, ADE7166, ADE7169 1 Not available in the ADE7116. Watt, VA, I , V ADE7116, ADE7166, ADE7169, ADE7566, rms rms ADE7569 Var ADE7169, ADE7569 di/dt Sensor ADE7169, ADE7569
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Document Outline GENERAL FEATURES ENERGY MEASUREMENT FEATURES MICROPROCESSOR FEATURES REVISION HISTORY GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAMS SPECIFICATIONS ENERGY METERING ANALOG PERIPHERALS DIGITAL INTERFACE TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS PERFORMANCE CURVES FOR THE ADE7169 AND ADE7569 ONLY TERMINOLOGY SPECIAL FUNCTION REGISTER (SFR) MAPPING POWER MANAGEMENT POWER MANAGEMENT REGISTER DETAILS Writing to the Interrupt Pins Configuration SFR (INTPR, Address 0xFF) Clearing the Scratch Pad Registers (SCRATCH1, Address 0xFB to SCRATCH4, Address 0xFE) Writing to the Power Control SFR (POWCON, Address 0xC5) POWER SUPPLY ARCHITECTURE BATTERY SWITCHOVER VDD to VBAT Switching from VBAT to VDD POWER SUPPLY MANAGEMENT (PSM) INTERRUPT Battery Switchover and Power Supply Restored PSM Interrupt VDCIN ADC PSM Interrupt VBAT Monitor PSM Interrupt VDCIN Monitor PSM Interrupt SAG Monitor PSM Interrupt USING THE POWER SUPPLY FEATURES OPERATING MODES PSM0 (NORMAL MODE) PSM1 (BATTERY MODE) PSM2 (SLEEP MODE) 3.3 V PERIPHERALS AND WAKE-UP EVENTS TRANSITIONING BETWEEN OPERATING MODES Automatic Battery Switchover (PSM0 to PSM1) Entering Sleep Mode (PSM1 to PSM2) Servicing Wake-Up Events (PSM2 to PSM1) Automatic Switch to VDD (PSM2 to PSM0) USING THE POWER MANAGEMENT FEATURES ENERGY MEASUREMENT ACCESS TO ENERGY MEASUREMENT SFRs ACCESS TO INTERNAL ENERGY MEASUREMENT REGISTERS Writing to the Internal Energy Measurement Registers Reading the Internal Energy Measurement Registers ENERGY MEASUREMENT REGISTERS ENERGY MEASUREMENT INTERNAL REGISTER DETAILS INTERRUPT STATUS/ENABLE SFRs ANALOG INPUTS ANALOG-TO-DIGITAL CONVERSION Antialiasing Filter ADC Transfer Function Current Channel ADC Voltage Channel ADC Channel Sampling FAULT DETECTION Channel Selection Indication Fault Indication Fault with Active Input Greater Than Inactive Input Fault with Inactive Input Greater Than Active Input Calibration Concerns di/dt CURRENT SENSOR AND DIGITAL INTEGRATOR FOR THE ADE7169/ADE7569 POWER QUALITY MEASUREMENTS Zero-Crossing Detection Zero-Crossing Timeout Period or Frequency Measurements Line Voltage SAG Detection SAG Level Set Peak Detection Peak Level Set Peak Level Record PHASE COMPENSATION RMS CALCULATION Current Channel RMS Calculation Current Channel RMS Offset Compensation Voltage Channel RMS Calculation Voltage Channel RMS Offset Compensation ACTIVE POWER CALCULATION Active Power Gain Calibration Active Power Offset Calibration Active Power Sign Detection Active Power No Load Detection ACTIVE ENERGY CALCULATION Integration Time Under Steady Load: Active Energy Active Energy Accumulation Modes Watt Signed Accumulation Mode Watt Positive Only Accumulation Mode Watt Absolute Accumulation Mode Active Energy Pulse Output Line Cycle Active Energy Accumulation Mode REACTIVE POWER CALCULATION (ADE7169/ADE7569) Reactive Power Gain Calibration Reactive Power Offset Calibration Sign of Reactive Power Calculation Reactive Power Sign Detection Reactive Power No Load Detection REACTIVE ENERGY CALCULATION (ADE7169/ADE7569) Integration Time Under Steady Load: Reactive Energy Reactive Energy Accumulation Modes Var Signed Accumulation Mode Var Antitamper Accumulation Mode Var Absolute Accumulation Mode Reactive Energy Pulse Output Line Cycle Reactive Energy Accumulation Mode APPARENT POWER CALCULATION Apparent Power Offset Calibration APPARENT ENERGY CALCULATION Integration Time Under Steady Load: Apparent Energy Apparent Energy Pulse Output Line Apparent Energy Accumulation Apparent Power No Load Detection AMPERE HOUR ACCUMULATION ENERGY TO FREQUENCY CONVERSION Pulse Output Configuration Pulse Output Characteristic ENERGY REGISTER SCALING ENERGY MEASUREMENT INTERRUPTS TEMPERATURE, BATTERY, AND SUPPLY VOLTAGE MEASUREMENTS TEMPERATURE MEASUREMENT Single Temperature Measurement Background Temperature Measurements Temperature ADC in PSM0, PSM1, and PSM2 Temperature ADC Interrupt BATTERY MEASUREMENT Single Battery Measurement Background Battery Measurements Battery ADC in PSM0, PSM1, and PSM2 Modes Battery ADC Interrupt EXTERNAL VOLTAGE MEASUREMENT Single External Voltage Measurement Background External Voltage Measurements External Voltage ADC in PSM0, PSM1, and PSM2 Modes External Voltage ADC Interrupt 8052 MCU CORE ARCHITECTURE MCU REGISTERS BASIC 8052 REGISTERS Program Counter (PC) Instruction Register (IR) Register Banks Accumulator B Register Program Status Word (PSW) Data Pointer (DPTR) Stack Pointer (SP) STANDARD 8052 SFRs Timer SFRs Serial Port SFRs Interrupt SFRs I/O Port SFRs Power Control Register (PCON, Address 0x87) MEMORY OVERVIEW General-Purpose RAM Special Function Registers (SFRs) Extended Internal RAM (XRAM) Code Memory ADDRESSING MODES Immediate Addressing Direct Addressing Indirect Addressing Extended Direct Addressing Extended Indirect Addressing Code Indirect Addressing INSTRUCTION SET READ-MODIFY-WRITE INSTRUCTIONS INSTRUCTIONS THAT AFFECT FLAGS ADD A, Source ADDC A, Source SUBB A, Source MUL AB DIV AB DA A RRC A RLC A CJNE Destination, Source, Relative Jump DUAL DATA POINTERS INTERRUPT SYSTEM STANDARD 8052 INTERRUPT ARCHITECTURE INTERRUPT ARCHITECTURE INTERRUPT REGISTERS INTERRUPT PRIORITY INTERRUPT FLAGS INTERRUPT VECTORS INTERRUPT LATENCY CONTEXT SAVING WATCHDOG TIMER Writing to the Watchdog Timer SFR (WDCON, Address 0xC0) Watchdog Timer Interrupt LCD DRIVER LCD REGISTERS LCD SETUP LCD TIMING AND WAVEFORMS BLINK MODE Software Controlled Blink Mode Automatic Blink Mode DISPLAY ELEMENT CONTROL Writing to LCD Data Registers Reading LCD Data Registers VOLTAGE GENERATION Lifetime Performance Power Consumption Contrast Control Lifetime Performance LCD EXTERNAL CIRCUITRY Charge Pump External Resistor Ladder LCD FUNCTION IN PSM2 MODE Example LCD Setup FLASH MEMORY FLASH MEMORY OVERVIEW Flash/EE Memory Reliability FLASH MEMORY ORGANIZATION USING THE FLASH MEMORY ECON—Flash Control SFR Flash Functions Write Byte Erase Page Erase All Read Byte Erase Page and Write Byte PROTECTING THE FLASH MEMORY Enabling Flash Protection by Code Enabling Flash Protection by Emulator Commands Notes on Flash Protection Flash Memory Timing IN CIRCUIT PROGRAMMING Serial Downloading TIMERS TIMER REGISTERS TIMER 0 AND TIMER 1 Timer 0 High/Low and Timer 1 High/Low Data SFRs Timer/Counter 0 and Timer/Counter 1 Operating Modes Mode 0 (13-Bit Timer/Counter) Mode 1 (16-Bit Timer/Counter) Mode 2 (8-Bit Timer/Counter with Autoreload) Mode 3 (Two 8-Bit Timer/Counters) TIMER 2 Timer/Counter 2 Data Registers Timer/Counter 2 Operating Modes 16-Bit Autoreload Mode 16-Bit Capture Mode PHASE-LOCKED LOOP (PLL) PLL REGISTERS REAL-TIME CLOCK (RTC) RTC SFRS Protecting the RTC from Runaway Code READ AND WRITE OPERATIONS Writing to the RTC Registers Reading the RTC Counter SFRs RTC MODES RTC INTERRUPTS Interval Timer Alarm RTC CALIBRATION Calibrating the RTC Calibration Flow UART SERIAL INTERFACE UART SFRS UART OPERATION MODES Mode 0 (Shift Register with Baud Rate Fixed at fCORE/12) Mode 1 (8-Bit UART, Variable Baud Rate) Mode 2 (9-Bit UART with Baud Fixed at fCORE/64 or fCORE/32) Mode 3 (9-Bit UART with Variable Baud Rate) UART BAUD RATE GENERATION Mode 0 Baud Rate Generation Mode 2 Baud Rate Generation Mode 1 and Mode 3 Baud Rate Generation Timer 1 Generated Baud Rates Timer 2 Generated Baud Rates UART Timer Generated Baud Rates UART ADDITIONAL FEATURES Enhanced Error Checking UART TxD Signal Modulation SERIAL PERIPHERAL INTERFACE (SPI) SPI REGISTERS SPI PINS MISO (Master In, Slave Out Data I/O Pin) MOSI (Master Out, Slave In Pin) SCLK (Serial Clock I/O Pin) /SS (Slave Select Pin) SPI MASTER OPERATING MODES Procedures for Using SPI as a Master Single Byte Write Mode, SPICONT (SPIMOD2[7]) = 0 Continuous Mode, SPICONT (SPIMOD2[7]) = 1 SPI INTERRUPT AND STATUS FLAGS I2C-COMPATIBLE INTERFACE SERIAL CLOCK GENERATION SLAVE ADDRESSES I2C REGISTERS READ AND WRITE OPERATIONS Reading the SPI/I2C Receive Buffer SFR (SPI2CRx, Address 0x9B) I2C RECEIVE AND TRANSMIT FIFOS I/O PORTS PARALLEL I/O Weak Internal Pull-Ups Enabled Open Drain (Weak Internal Pull-Ups Disabled) 38 kHz Modulation I/O REGISTERS PORT 0 PORT 1 PORT 2 DETERMINING THE VERSION OF THE DEVICE OUTLINE DIMENSIONS ORDERING GUIDE