Datasheet ADE7116, ADE7166, ADE7169, ADE7566, ADE7569 (Analog Devices) - 10

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ADE7116/ADE7166/ADE7169/ADE7566/ADE7569 Data Sheet TIMING SPECIFICATIONS
AC inputs during testing were driven at VSWOUT − 0.5 V for Logic 1 For timing purposes, a port pin is no longer floating when a and at 0.45 V for Logic 0. Timing measurements were made at VIH 100 mV change from load voltage occurs. A port pin begins to minimum for Logic 1 and at VIL maximum for Logic 0, as shown in float when a 100 mV change from the loaded VOH/VOL level Figure 3. occurs, as shown in Figure 3. CLOAD for all outputs is equal to 80 pF, unless otherwise noted. VDD = 2.7 V to 3.6 V; all specifications TMIN to TMAX, unless otherwise noted.
VSWOUT – 0.5V 0.2V V V SWOUT + 0.9V LOAD – 0.1V TIMING LOAD – 0.1V TEST POINTS VLOAD REFERENCE VLOAD 0.2V POINTS
002
SWOUT – 0.1V VLOAD + 0.1V VLOAD – 0.1V 0.45V
06353- Figure 3. Timing Waveform Characteristics
Table 5. Clock Input (External Clock Driven XTAL1) Parameter 32.768 kHz External Crystal Parameter Description Min Typ Max Unit
t XTAL1 period 30.52 µs CK t XTAL1 width low 6.26 µs CKL t XTAL1 width high 6.26 µs CKH t XTAL1 rise time 9 ns CKR t XTAL1 fall time 9 ns CKF 1/t Core clock frequency1 1.024 MHz CORE 1 The internal PLL locks onto a multiple (512×) of the 32.768 kHz external crystal frequency to provide a stable 4.096 MHz internal clock for the system. The core can operate at this frequency or at a binary submultiple defined by the CD bits of the POWCON SFR, Address 0xC5[2:0] (see Table 26).
Table 6. I2C Compatible Interface Timing Parameters (400 kHz) Parameter Description Typ Unit
t Bus free time between stop condition and start condition 1.3 µs BUF t SCLK low pulse width 1.36 µs L t SCLK high pulse width 1.14 µs H t Start condition hold time 251.35 µs SHD t Data setup time 740 ns DSU t Data hold time 400 ns DHD t Setup time for repeated start 12.5 ns RSU t Stop condition setup time 400 ns PSU t Rise time of both SCLK and SDATA 200 ns R t Fall time of both SCLK and SDATA 300 ns F t 1 Pulse width of spike suppressed 50 ns SUP 1 Input filtering on both the SCLK and SDATA inputs suppresses noise spikes of <50 ns.
tBUF tSUP tR SDATA (I/O) MSB LSB ACK MSB tDSU tDSU tF t t DHD DHD tR t t t PSU t RSU SHD H SCLK (I) 1 8 9 1 2 TO 7 t t PS L SUP S(R) tF
003
STOP START REPEATED CONDITION CONDITION START
06353- Figure 4. I2C Compatible Interface Timing Rev. C | Page 10 of 152 Document Outline GENERAL FEATURES ENERGY MEASUREMENT FEATURES MICROPROCESSOR FEATURES REVISION HISTORY GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAMS SPECIFICATIONS ENERGY METERING ANALOG PERIPHERALS DIGITAL INTERFACE TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS PERFORMANCE CURVES FOR THE ADE7169 AND ADE7569 ONLY TERMINOLOGY SPECIAL FUNCTION REGISTER (SFR) MAPPING POWER MANAGEMENT POWER MANAGEMENT REGISTER DETAILS Writing to the Interrupt Pins Configuration SFR (INTPR, Address 0xFF) Clearing the Scratch Pad Registers (SCRATCH1, Address 0xFB to SCRATCH4, Address 0xFE) Writing to the Power Control SFR (POWCON, Address 0xC5) POWER SUPPLY ARCHITECTURE BATTERY SWITCHOVER VDD to VBAT Switching from VBAT to VDD POWER SUPPLY MANAGEMENT (PSM) INTERRUPT Battery Switchover and Power Supply Restored PSM Interrupt VDCIN ADC PSM Interrupt VBAT Monitor PSM Interrupt VDCIN Monitor PSM Interrupt SAG Monitor PSM Interrupt USING THE POWER SUPPLY FEATURES OPERATING MODES PSM0 (NORMAL MODE) PSM1 (BATTERY MODE) PSM2 (SLEEP MODE) 3.3 V PERIPHERALS AND WAKE-UP EVENTS TRANSITIONING BETWEEN OPERATING MODES Automatic Battery Switchover (PSM0 to PSM1) Entering Sleep Mode (PSM1 to PSM2) Servicing Wake-Up Events (PSM2 to PSM1) Automatic Switch to VDD (PSM2 to PSM0) USING THE POWER MANAGEMENT FEATURES ENERGY MEASUREMENT ACCESS TO ENERGY MEASUREMENT SFRs ACCESS TO INTERNAL ENERGY MEASUREMENT REGISTERS Writing to the Internal Energy Measurement Registers Reading the Internal Energy Measurement Registers ENERGY MEASUREMENT REGISTERS ENERGY MEASUREMENT INTERNAL REGISTER DETAILS INTERRUPT STATUS/ENABLE SFRs ANALOG INPUTS ANALOG-TO-DIGITAL CONVERSION Antialiasing Filter ADC Transfer Function Current Channel ADC Voltage Channel ADC Channel Sampling FAULT DETECTION Channel Selection Indication Fault Indication Fault with Active Input Greater Than Inactive Input Fault with Inactive Input Greater Than Active Input Calibration Concerns di/dt CURRENT SENSOR AND DIGITAL INTEGRATOR FOR THE ADE7169/ADE7569 POWER QUALITY MEASUREMENTS Zero-Crossing Detection Zero-Crossing Timeout Period or Frequency Measurements Line Voltage SAG Detection SAG Level Set Peak Detection Peak Level Set Peak Level Record PHASE COMPENSATION RMS CALCULATION Current Channel RMS Calculation Current Channel RMS Offset Compensation Voltage Channel RMS Calculation Voltage Channel RMS Offset Compensation ACTIVE POWER CALCULATION Active Power Gain Calibration Active Power Offset Calibration Active Power Sign Detection Active Power No Load Detection ACTIVE ENERGY CALCULATION Integration Time Under Steady Load: Active Energy Active Energy Accumulation Modes Watt Signed Accumulation Mode Watt Positive Only Accumulation Mode Watt Absolute Accumulation Mode Active Energy Pulse Output Line Cycle Active Energy Accumulation Mode REACTIVE POWER CALCULATION (ADE7169/ADE7569) Reactive Power Gain Calibration Reactive Power Offset Calibration Sign of Reactive Power Calculation Reactive Power Sign Detection Reactive Power No Load Detection REACTIVE ENERGY CALCULATION (ADE7169/ADE7569) Integration Time Under Steady Load: Reactive Energy Reactive Energy Accumulation Modes Var Signed Accumulation Mode Var Antitamper Accumulation Mode Var Absolute Accumulation Mode Reactive Energy Pulse Output Line Cycle Reactive Energy Accumulation Mode APPARENT POWER CALCULATION Apparent Power Offset Calibration APPARENT ENERGY CALCULATION Integration Time Under Steady Load: Apparent Energy Apparent Energy Pulse Output Line Apparent Energy Accumulation Apparent Power No Load Detection AMPERE HOUR ACCUMULATION ENERGY TO FREQUENCY CONVERSION Pulse Output Configuration Pulse Output Characteristic ENERGY REGISTER SCALING ENERGY MEASUREMENT INTERRUPTS TEMPERATURE, BATTERY, AND SUPPLY VOLTAGE MEASUREMENTS TEMPERATURE MEASUREMENT Single Temperature Measurement Background Temperature Measurements Temperature ADC in PSM0, PSM1, and PSM2 Temperature ADC Interrupt BATTERY MEASUREMENT Single Battery Measurement Background Battery Measurements Battery ADC in PSM0, PSM1, and PSM2 Modes Battery ADC Interrupt EXTERNAL VOLTAGE MEASUREMENT Single External Voltage Measurement Background External Voltage Measurements External Voltage ADC in PSM0, PSM1, and PSM2 Modes External Voltage ADC Interrupt 8052 MCU CORE ARCHITECTURE MCU REGISTERS BASIC 8052 REGISTERS Program Counter (PC) Instruction Register (IR) Register Banks Accumulator B Register Program Status Word (PSW) Data Pointer (DPTR) Stack Pointer (SP) STANDARD 8052 SFRs Timer SFRs Serial Port SFRs Interrupt SFRs I/O Port SFRs Power Control Register (PCON, Address 0x87) MEMORY OVERVIEW General-Purpose RAM Special Function Registers (SFRs) Extended Internal RAM (XRAM) Code Memory ADDRESSING MODES Immediate Addressing Direct Addressing Indirect Addressing Extended Direct Addressing Extended Indirect Addressing Code Indirect Addressing INSTRUCTION SET READ-MODIFY-WRITE INSTRUCTIONS INSTRUCTIONS THAT AFFECT FLAGS ADD A, Source ADDC A, Source SUBB A, Source MUL AB DIV AB DA A RRC A RLC A CJNE Destination, Source, Relative Jump DUAL DATA POINTERS INTERRUPT SYSTEM STANDARD 8052 INTERRUPT ARCHITECTURE INTERRUPT ARCHITECTURE INTERRUPT REGISTERS INTERRUPT PRIORITY INTERRUPT FLAGS INTERRUPT VECTORS INTERRUPT LATENCY CONTEXT SAVING WATCHDOG TIMER Writing to the Watchdog Timer SFR (WDCON, Address 0xC0) Watchdog Timer Interrupt LCD DRIVER LCD REGISTERS LCD SETUP LCD TIMING AND WAVEFORMS BLINK MODE Software Controlled Blink Mode Automatic Blink Mode DISPLAY ELEMENT CONTROL Writing to LCD Data Registers Reading LCD Data Registers VOLTAGE GENERATION Lifetime Performance Power Consumption Contrast Control Lifetime Performance LCD EXTERNAL CIRCUITRY Charge Pump External Resistor Ladder LCD FUNCTION IN PSM2 MODE Example LCD Setup FLASH MEMORY FLASH MEMORY OVERVIEW Flash/EE Memory Reliability FLASH MEMORY ORGANIZATION USING THE FLASH MEMORY ECON—Flash Control SFR Flash Functions Write Byte Erase Page Erase All Read Byte Erase Page and Write Byte PROTECTING THE FLASH MEMORY Enabling Flash Protection by Code Enabling Flash Protection by Emulator Commands Notes on Flash Protection Flash Memory Timing IN CIRCUIT PROGRAMMING Serial Downloading TIMERS TIMER REGISTERS TIMER 0 AND TIMER 1 Timer 0 High/Low and Timer 1 High/Low Data SFRs Timer/Counter 0 and Timer/Counter 1 Operating Modes Mode 0 (13-Bit Timer/Counter) Mode 1 (16-Bit Timer/Counter) Mode 2 (8-Bit Timer/Counter with Autoreload) Mode 3 (Two 8-Bit Timer/Counters) TIMER 2 Timer/Counter 2 Data Registers Timer/Counter 2 Operating Modes 16-Bit Autoreload Mode 16-Bit Capture Mode PHASE-LOCKED LOOP (PLL) PLL REGISTERS REAL-TIME CLOCK (RTC) RTC SFRS Protecting the RTC from Runaway Code READ AND WRITE OPERATIONS Writing to the RTC Registers Reading the RTC Counter SFRs RTC MODES RTC INTERRUPTS Interval Timer Alarm RTC CALIBRATION Calibrating the RTC Calibration Flow UART SERIAL INTERFACE UART SFRS UART OPERATION MODES Mode 0 (Shift Register with Baud Rate Fixed at fCORE/12) Mode 1 (8-Bit UART, Variable Baud Rate) Mode 2 (9-Bit UART with Baud Fixed at fCORE/64 or fCORE/32) Mode 3 (9-Bit UART with Variable Baud Rate) UART BAUD RATE GENERATION Mode 0 Baud Rate Generation Mode 2 Baud Rate Generation Mode 1 and Mode 3 Baud Rate Generation Timer 1 Generated Baud Rates Timer 2 Generated Baud Rates UART Timer Generated Baud Rates UART ADDITIONAL FEATURES Enhanced Error Checking UART TxD Signal Modulation SERIAL PERIPHERAL INTERFACE (SPI) SPI REGISTERS SPI PINS MISO (Master In, Slave Out Data I/O Pin) MOSI (Master Out, Slave In Pin) SCLK (Serial Clock I/O Pin) /SS (Slave Select Pin) SPI MASTER OPERATING MODES Procedures for Using SPI as a Master Single Byte Write Mode, SPICONT (SPIMOD2[7]) = 0 Continuous Mode, SPICONT (SPIMOD2[7]) = 1 SPI INTERRUPT AND STATUS FLAGS I2C-COMPATIBLE INTERFACE SERIAL CLOCK GENERATION SLAVE ADDRESSES I2C REGISTERS READ AND WRITE OPERATIONS Reading the SPI/I2C Receive Buffer SFR (SPI2CRx, Address 0x9B) I2C RECEIVE AND TRANSMIT FIFOS I/O PORTS PARALLEL I/O Weak Internal Pull-Ups Enabled Open Drain (Weak Internal Pull-Ups Disabled) 38 kHz Modulation I/O REGISTERS PORT 0 PORT 1 PORT 2 DETERMINING THE VERSION OF THE DEVICE OUTLINE DIMENSIONS ORDERING GUIDE