Datasheet ADE7761B (Analog Devices) - 4

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ADE7761B Parameter Value Unit Test Conditions/Comments
LOGIC INPUTS5 PGA, SCF, S1, and S0 Input High Voltage, VINH 2.4 V, min VDD = 5 V ± 5% Input Low Voltage, VINL 0.8 V, max VDD = 5 V ± 5% Input Current, IIN ±3 μA, max Typical 10 nA, VIN = 0 V to VDD Input Capacitance, CIN 10 pF, max LOGIC OUTPUTS5 CF, REVP, and FAULT Output High Voltage, VOH 4 V, min VDD = 5 V ± 5% Output Low Voltage, VOH 1 V, max VDD = 5 V ± 5% F1 and F2 Output High Voltage, VOH 4 V, min VDD = 5 V ± 5%, ISOURCE = 10 mA Output Low Voltage, VOH 1 V, max VDD = 5 V ± 5%, ISINK = 10 mA POWER SUPPLY For specified performance VDD 4.75 V, min 5 V − 5% 5.25 V, max 5 V + 5% IDD 3.65 mA, max 1 See plots in the Typical Performance Characteristics section. 2 See the Terminology section for explanation of specifications. 3 See the Fault Detection section for explanation of fault detection functionality. 4 See the Missing Neutral Detection section for explanation of missing neutral detection functionality. 5 Sample tested during initial release and after any redesign or process change that might affect this parameter.
TIMING CHARACTERISTICS
VDD = 5 V ± 5%, AGND = DGND = 0 V, on-chip reference, on-chip oscillator, TMIN to TMAX = −40°C to +85°C. Sample tested during initial release and after any redesign or process change that might affect this parameter. See Figure 2.
Table 2. Parameter Value Unit Test Conditions/Comments
t 1 1 120 ms F1 and F2 pulse width (logic high) t2 See Table 8 sec Output pulse period (see the Transfer Function section) t3 1/2 t2 sec Time between F1 falling edge and F2 falling edge t 1 4 90 ms CF pulse width (logic high) t5 See Table 8 sec CF pulse period (see the Transfer Function section) t6 CLKIN/4 sec Minimum time between F1 pulse and F2 pulse 1 The pulse widths of F1, F2, and CF are not fixed for higher output frequencies. See the Transfer Function section.
Timing Diagram t1 F1 t6 t2 t3 F2 t4 t5
02 0 7-
CF
679 0 Figure 2. Timing Diagram for Frequency Outputs Rev. 0 | Page 4 of 24 Document Outline FEATURES GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING CHARACTERISTICS Timing Diagram ABSOLUTE MAXIMUM RATINGS PERFORMANCE ISSUES THAT MAY AFFECT BILLING ACCURACY Case 1 Case 2 ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TEST CIRCUIT TERMINOLOGY THEORY OF OPERATION POWER SUPPLY MONITOR ANALOG INPUTS Channel V1 (Current Channel) Channel V2 (Voltage Channel) MISCAL Input Typical Connection Diagrams INTERNAL OSCILLATOR ANALOG-TO-DIGITAL CONVERSION Antialias Filter ACTIVE POWER CALCULATION Power Factor Considerations Nonsinusoidal Voltage and Current HPF and Offset Effects DIGITAL-TO-FREQUENCY CONVERSION TRANSFER FUNCTION Frequency Output F1 and Frequency Output F2 Frequency Output CF FAULT DETECTION Fault with Active Input Greater Than Inactive Input Fault with Inactive Input Greater Than Active Input Calibration Concerns MISSING NEUTRAL MODE Important Note for Billing of Active Energy Missing Neutral Detection Missing Neutral Gain Calibration APPLICATIONS INFORMATION INTERFACING TO A MICROCONTROLLER FOR ENERGY MEASUREMENT SELECTING A FREQUENCY FOR AN ENERGY METER APPLICATION Frequency Outputs No-Load Threshold NEGATIVE POWER INFORMATION OUTLINE DIMENSIONS ORDERING GUIDE