Datasheet LTC1150 (Analog Devices) - 10
| 制造商 | Analog Devices |
| 描述 | ±15V Zero-Drift Operational Amplifier with Internal Capacitors |
| 页数 / 页 | 16 / 10 — APPLICATIO S I FOR ATIO. Table 1. Resistor Thermal EMF. LEVEL SHIFTING … |
| 文件格式/大小 | PDF / 245 Kb |
| 文件语言 | 英语 |
APPLICATIO S I FOR ATIO. Table 1. Resistor Thermal EMF. LEVEL SHIFTING THE CLOCK. RESISTOR TYPE. THERMAL EMF/. C GRADIENT
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LTC1150
U U W U APPLICATIO S I FOR ATIO Table 1. Resistor Thermal EMF LEVEL SHIFTING THE CLOCK RESISTOR TYPE THERMAL EMF/
°
C GRADIENT
Level shifting is needed if the clock output of the LTC1150 Tin Oxide ~mV/°C in ±15V operation must interface to regular 5V logic Carbon Composition ~450µV/°C circuits. Figures 2 and 3 show some typical level shifting Metal Film ~20µV/°C circuits. WireWound When operated from single 5V or ±5V supplies, the Evenohm ~2µV/°C LTC1150 clock output at Pin 8 can interface to TTL or Manganin ~2µV/°C CMOS inputs directly.
PACKAGE-INDUCED OFFSET VOLTAGE
Package-induced thermal EMF effects are another impor-
LOW SUPPLY OPERATION
tant source of errors. It arises at the copper/kovar The minimum supply for proper operation of the LTC1150 junctions formed when wire or printed circuit traces is typically below 4.0V (±2.0V). In single supply applica- contact a package lead. Like all the previously mentioned tions, PSRR is guaranteed down to 4.7V (±2.35V) thermal EMF effects, it is outside the LTC1150’s offset to ensure proper operation down to the minimum TTL nulling loop and cannot be cancelled. Metal can specified voltage of 4.75V. H packages exhibit the worst warm-up drift. The input offset voltage specification of the LTC1150 is actually set 15V by the package-induced warm-up drift rather than by the circuit itself. The thermal time constant ranges from 0.5 to 10k 3 minutes, depending on package type. 7 5V 2 – 8 6
ALIASING
LTC1150 3 LOGIC + CIRCUIT Like all sampled data systems, the LTC1150 exhibits 4 10k aliasing behavior at input frequencies near the sampling frequency. The LTC1150 includes a high-frequency –15V LTC1150 • AI02 correction loop which minimizes this effect; as a result, aliasing is not a problem for most applications.
Figure 2. Output Level Shift (Option 1)
For a complete discussion of the correction circuitry and aliasing behavior, please refer to the LTC1051/53 data sheet. 15V 5V 5V 100pF 10k
SYNCHRONIZATION OF MULTIPLE LTC115O’S
2 7 – 8 LOGIC When synchronization of several LTC1150’s is required, 6 CIRCUIT LTC1150 one of the LTC1150’s can be used to provide the “master” 3 + clock to control over 100 “slave” LTC1150’s. The master 4 10k clock, coming from Pin 8 of the master LTC1150, can –15V directly drive Pin 5 of the slaves. Note that Pin 8 of the slave LTC1150 • AI03 GND LTC1150’s will be pulled up to VS.
Figure 3. Output Level Shift (Option 2)
If all the LTC1150’s are to be synchronized with an external clock, then the external clock should drive Pin 5 of all the LTC1150’s. 1150fb 10
U U W U APPLICATIO S I FOR ATIO Table 1. Resistor Thermal EMF LEVEL SHIFTING THE CLOCK RESISTOR TYPE THERMAL EMF/
°
C GRADIENT
Level shifting is needed if the clock output of the LTC1150 Tin Oxide ~mV/°C in ±15V operation must interface to regular 5V logic Carbon Composition ~450µV/°C circuits. Figures 2 and 3 show some typical level shifting Metal Film ~20µV/°C circuits. WireWound When operated from single 5V or ±5V supplies, the Evenohm ~2µV/°C LTC1150 clock output at Pin 8 can interface to TTL or Manganin ~2µV/°C CMOS inputs directly.
PACKAGE-INDUCED OFFSET VOLTAGE
Package-induced thermal EMF effects are another impor-
LOW SUPPLY OPERATION
tant source of errors. It arises at the copper/kovar The minimum supply for proper operation of the LTC1150 junctions formed when wire or printed circuit traces is typically below 4.0V (±2.0V). In single supply applica- contact a package lead. Like all the previously mentioned tions, PSRR is guaranteed down to 4.7V (±2.35V) thermal EMF effects, it is outside the LTC1150’s offset to ensure proper operation down to the minimum TTL nulling loop and cannot be cancelled. Metal can specified voltage of 4.75V. H packages exhibit the worst warm-up drift. The input offset voltage specification of the LTC1150 is actually set 15V by the package-induced warm-up drift rather than by the circuit itself. The thermal time constant ranges from 0.5 to 10k 3 minutes, depending on package type. 7 5V 2 – 8 6
ALIASING
LTC1150 3 LOGIC + CIRCUIT Like all sampled data systems, the LTC1150 exhibits 4 10k aliasing behavior at input frequencies near the sampling frequency. The LTC1150 includes a high-frequency –15V LTC1150 • AI02 correction loop which minimizes this effect; as a result, aliasing is not a problem for most applications.
Figure 2. Output Level Shift (Option 1)
For a complete discussion of the correction circuitry and aliasing behavior, please refer to the LTC1051/53 data sheet. 15V 5V 5V 100pF 10k
SYNCHRONIZATION OF MULTIPLE LTC115O’S
2 7 – 8 LOGIC When synchronization of several LTC1150’s is required, 6 CIRCUIT LTC1150 one of the LTC1150’s can be used to provide the “master” 3 + clock to control over 100 “slave” LTC1150’s. The master 4 10k clock, coming from Pin 8 of the master LTC1150, can –15V directly drive Pin 5 of the slaves. Note that Pin 8 of the slave LTC1150 • AI03 GND LTC1150’s will be pulled up to VS.
Figure 3. Output Level Shift (Option 2)
If all the LTC1150’s are to be synchronized with an external clock, then the external clock should drive Pin 5 of all the LTC1150’s. 1150fb 10