Datasheet LT1057, LT1058 (Analog Devices) - 9

LT1057/LT1058
APPLICATIONS INFORMATION
Settling time is measured in a test circuit which can be Offset voltage also changes somewhat with temperature found in the LT1055/LT1056 data sheet and in Application cycling. The AM grades show a typical 40µV hysteresis Note 10. (50µV on the M grades) when cycled over the –55°C to 125°C temperature range. Temperature cycling from 0°C to
Achieving Picoampere/Microvolt Performance
70°C has a negligible (less than 20µV) hysteresis effect. In order to realize the picoampere/microvolt level accuracy The offset voltage and drift performance are also affected of the LT1057/LT1058, proper care must be exercised. For by packaging. In the plastic N package, the molding com- example, leakage currents in circuitry external to the op pound is in direct contact with the chip, exerting pressure amp can significantly degrade performance. High quality on the surface. While NPN input transistors are largely insulation should be used (e.g., TeflonTM, Kel-F); cleaning unaffected by this pressure, JFET device drift is degraded. of all insulating surfaces to remove fluxes and other resi- Consequently for best drift performance, as shown in the dues will probably be required. Surface coating may be Typical Performance Characteristics distribution plots, the necessary to provide a moisture barrier in high humidity J or H packages are recommended. environments. In applications where speed and picoampere bias currents Board leakage can be minimized by encircling the input are not necessary, Linear Technology offers the bipolar circuitry with a guard ring operated at a potential close to input, pin compatible LT1013 and LT1014 dual and quad that of the inputs; in inverting configurations, the guard op amps. These devices have significantly better DC ring should be tied to ground, in noninverting connections, specifications than any JFET input device. to the inverting input. Guarding both sides of the printed circuit board is required. Bulk leakage reduction depends
Phase Reversal Protection
on the guard ring width. Most industry standard JFET input single, dual and quad The LT1057/LT1058 have the lowest offset voltage of any op amps (e.g., LF156, LF351, LF353, LF411, LF412, dual and quad JFET input op amps available today. However, OP-15, OP-16, OP-215, TL084) exhibit phase reversal at the offset voltage and its drift with time and temperature are the output when the negative common mode limit at the still not as good as on the best bipolar amplifiers (because input is exceeded (i.e., below –12V with ±15V supplies). the transconductance of FETs is considerably lower than The photos below show a ±16V sine wave input (A), the that of bipolar transistors). Conversely, this lower trans- response of an LF412A in the unity gain follower mode conductance is the main cause of the significantly faster (B), and the response of the LT1057/LT1058 (C). speed performance of FET input op amps. The phase reversal of photo (B) can cause lock-up in servo systems. The LT1057/LT1058 does not phase-reverse due Teflon is a trademark of DuPont. to a unique phase reversal protection circuit.
(A) ±16V Sine Wave Input (B) LF412A Output (C) LT1057/LT1058 Output All Photos 5V/Div Vertical Scale, 50µs/Div Horizontal Scale
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