Datasheet LTC1052, LTC7652 (Analog Devices) - 10
| 制造商 | Analog Devices |
| 描述 | Zero-Drift Operational Amplifier |
| 页数 / 页 | 24 / 10 — APPLICATIO S I FOR ATIO. Figure 3. Offset Drift Test Circuit |
| 文件格式/大小 | PDF / 871 Kb |
| 文件语言 | 英语 |
APPLICATIO S I FOR ATIO. Figure 3. Offset Drift Test Circuit
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LTC1052/LTC7652
U U W U APPLICATIO S I FOR ATIO
When all of these errors are considered, it may seem Figure 4 shows the response of this circuit under impossible to take advantage of the extremely low drift temperature transient conditions. Metal film resistors and specifications of the LTC1052. To show that this is not the an 8-pin DIP socket were used. Care was taken in the case, examine the temperature test circuit of Figure 3. The construction to thermally balance the inputs to the lead lengths of the resistors connected to the amplifier’s amplifier. The units were placed in an oven and allowed to inputs are identical. The thermal capacity and thermal stabilize at 25°C. The recording was started and after resistance each input sees is balanced because of the 100 seconds the oven, preset to 125°C, was switched on. symmetrical connection of resistors and their identical The test was first performed on an 8-pin plastic package size. Thermal EMF-induced shifts are equal in phase and and then was repeated for a TO-5 package plugged into the amplitude, thus cancellation occurs. same test board. It is significant that the change in VOS, even under these severe thermal transient conditions, 50k is quite good. As temperature stabilizes, note that the 5V steady-state change of V 2 7 OS is well within the maximum – 6 ±0.05µV/°C drift specification. 100Ω LTC1052 3 8 + 4 V Very slight air currents can still affect even this 1 OS • 1000 0.1µF 50k arrangement. Figure 5 shows strip charts of output noise 0.1µF 0.1µF both with the circuit covered and with no cover in “still” air. –5V LTC1052/7652 • AI04 This data illustrates why it is often prudent to enclose the LTC1052 and its attendant components inside some form
Figure 3. Offset Drift Test Circuit
of thermal baffle. 0 MIN 5 MIN 20 MIN 25 MIN 10 25°C TO 125°C PLASTIC 0 ±0.05µV/°C V/DIV) µ (10 OS 10 OFFSET VOLTAGE, V 25°C TO 125°C METAL CAN 0 ±0.05µV/°C OVEN SWITCHED OVEN STABILIZED ON (25°C) AT 12 MIN 100 SECONDS/IN
Figure 4. Transient Response of Offset Drift Test Circuit with 100
°
C Temperature Step
1052fa 10
U U W U APPLICATIO S I FOR ATIO
When all of these errors are considered, it may seem Figure 4 shows the response of this circuit under impossible to take advantage of the extremely low drift temperature transient conditions. Metal film resistors and specifications of the LTC1052. To show that this is not the an 8-pin DIP socket were used. Care was taken in the case, examine the temperature test circuit of Figure 3. The construction to thermally balance the inputs to the lead lengths of the resistors connected to the amplifier’s amplifier. The units were placed in an oven and allowed to inputs are identical. The thermal capacity and thermal stabilize at 25°C. The recording was started and after resistance each input sees is balanced because of the 100 seconds the oven, preset to 125°C, was switched on. symmetrical connection of resistors and their identical The test was first performed on an 8-pin plastic package size. Thermal EMF-induced shifts are equal in phase and and then was repeated for a TO-5 package plugged into the amplitude, thus cancellation occurs. same test board. It is significant that the change in VOS, even under these severe thermal transient conditions, 50k is quite good. As temperature stabilizes, note that the 5V steady-state change of V 2 7 OS is well within the maximum – 6 ±0.05µV/°C drift specification. 100Ω LTC1052 3 8 + 4 V Very slight air currents can still affect even this 1 OS • 1000 0.1µF 50k arrangement. Figure 5 shows strip charts of output noise 0.1µF 0.1µF both with the circuit covered and with no cover in “still” air. –5V LTC1052/7652 • AI04 This data illustrates why it is often prudent to enclose the LTC1052 and its attendant components inside some form
Figure 3. Offset Drift Test Circuit
of thermal baffle. 0 MIN 5 MIN 20 MIN 25 MIN 10 25°C TO 125°C PLASTIC 0 ±0.05µV/°C V/DIV) µ (10 OS 10 OFFSET VOLTAGE, V 25°C TO 125°C METAL CAN 0 ±0.05µV/°C OVEN SWITCHED OVEN STABILIZED ON (25°C) AT 12 MIN 100 SECONDS/IN
Figure 4. Transient Response of Offset Drift Test Circuit with 100
°
C Temperature Step
1052fa 10