Datasheet LT1024 (Analog Devices) - 4
| 制造商 | Analog Devices |
| 描述 | Dual, Matched Picoampere, Microvolt Input, Low Noise Op Amp |
| 页数 / 页 | 12 / 4 — ELECTRICAL CHARACTERISTICS Matching Specifications. The. denotes the … |
| 文件格式/大小 | PDF / 179 Kb |
| 文件语言 | 英语 |
ELECTRICAL CHARACTERISTICS Matching Specifications. The. denotes the specifications which apply over
该数据表的模型线
文件文字版本
L T1 0 2 4
ELECTRICAL CHARACTERISTICS Matching Specifications. The
●
denotes the specifications which apply over the temperature range of 0
°
C
≤
TA = 70
°
C for the LT1024AC and LT1024C; – 55
°
C
≤
TA
≤
125
°
C for the LT1024AM and LT1024M, VS =
±
15V, VCM = 0V unless otherwise noted. LT1024AM/LT1024AC LT1024M/LT1024C SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS
Input Offset Voltage Match 0°C to 70°C ● 35 170 45 300 µV – 55°C to 125°C ● 50 280 70 500 µV Input Offset Voltage Tracking ● 0.3 2 0.4 3.5 µV/°C I + B Average Noninverting Bias Current 0°C to 70°C ● ±40 ±300 ±50 ±500 pA – 55°C to 125°C ● ±100 ±800 ±200 ±1400 pA I + OS Noninverting Offset Current 0°C to 70°C ● 40 300 50 500 pA – 55°C to 125°C ● 80 800 150 1500 pA ∆CMRR Common Mode Rejection Ratio Match VCM = ±13.5V ● 106 128 104 128 dB ∆PSRR Power Supply Rejection Ratio Match VS = ±2.5V to ±18V ● 106 128 104 128 dB
Note 1:
Absolute Maximum Ratings are those values beyond which the life
Optional Offset Nulling Circuit
of a device may be impaired.
Note 2:
Differential input voltages greater than 1V will cause excessive V+ current to flow through the input protection diodes unless limiting resistance is used. 5k TO 100k 1 (8) POT
Note 3:
The V+ supply terminals are completely independent and may be 2 (9) 3 powered by separate supplies if desired (this approach, however, would – 14 (7) (10) sacrifice the advantages of the power supply rejection ratio matching). The 13 1/2 LT1024 OUTPUT V– supply terminals are both connected to the common substrate and (6) 4 + must be tied to the same voltage. Both V– pins should be used. (11) 12 (5)
Note 4:
This parameter is tested on a sample basis only. INPUT OFFSET VOLTAGE CAN BE ADJUSTED V– OVER A ±800µV RANGE WITH A 5k TO 100k POTENTIOMETER LT1024 • EC01
W U TYPICAL PERFOR A CE CHARACTERISTICS Offset Voltage vs Source Input Offset Current vs Resistance (Balanced or Unbalanced) Temperature
1000 60 V V S = ±15V S = ±15V VCM = 0V 50 µV) 100 40 – 55°C TO 125°C 30 25°C 10 20 INPUT OFFSET VOLTAGE ( INPUT OFFSET CURRENT (pA) 10 1 0 1k 3k 10k 30k 100k 300k 1M 3M 10M – 50 –25 0 25 50 75 100 125 SOURCE RESISTANCE (Ω) TEMPERATURE (°C) LT1024 • TPC01 LT1024 • TPC02 1024fa 4
ELECTRICAL CHARACTERISTICS Matching Specifications. The
●
denotes the specifications which apply over the temperature range of 0
°
C
≤
TA = 70
°
C for the LT1024AC and LT1024C; – 55
°
C
≤
TA
≤
125
°
C for the LT1024AM and LT1024M, VS =
±
15V, VCM = 0V unless otherwise noted. LT1024AM/LT1024AC LT1024M/LT1024C SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS
Input Offset Voltage Match 0°C to 70°C ● 35 170 45 300 µV – 55°C to 125°C ● 50 280 70 500 µV Input Offset Voltage Tracking ● 0.3 2 0.4 3.5 µV/°C I + B Average Noninverting Bias Current 0°C to 70°C ● ±40 ±300 ±50 ±500 pA – 55°C to 125°C ● ±100 ±800 ±200 ±1400 pA I + OS Noninverting Offset Current 0°C to 70°C ● 40 300 50 500 pA – 55°C to 125°C ● 80 800 150 1500 pA ∆CMRR Common Mode Rejection Ratio Match VCM = ±13.5V ● 106 128 104 128 dB ∆PSRR Power Supply Rejection Ratio Match VS = ±2.5V to ±18V ● 106 128 104 128 dB
Note 1:
Absolute Maximum Ratings are those values beyond which the life
Optional Offset Nulling Circuit
of a device may be impaired.
Note 2:
Differential input voltages greater than 1V will cause excessive V+ current to flow through the input protection diodes unless limiting resistance is used. 5k TO 100k 1 (8) POT
Note 3:
The V+ supply terminals are completely independent and may be 2 (9) 3 powered by separate supplies if desired (this approach, however, would – 14 (7) (10) sacrifice the advantages of the power supply rejection ratio matching). The 13 1/2 LT1024 OUTPUT V– supply terminals are both connected to the common substrate and (6) 4 + must be tied to the same voltage. Both V– pins should be used. (11) 12 (5)
Note 4:
This parameter is tested on a sample basis only. INPUT OFFSET VOLTAGE CAN BE ADJUSTED V– OVER A ±800µV RANGE WITH A 5k TO 100k POTENTIOMETER LT1024 • EC01
W U TYPICAL PERFOR A CE CHARACTERISTICS Offset Voltage vs Source Input Offset Current vs Resistance (Balanced or Unbalanced) Temperature
1000 60 V V S = ±15V S = ±15V VCM = 0V 50 µV) 100 40 – 55°C TO 125°C 30 25°C 10 20 INPUT OFFSET VOLTAGE ( INPUT OFFSET CURRENT (pA) 10 1 0 1k 3k 10k 30k 100k 300k 1M 3M 10M – 50 –25 0 25 50 75 100 125 SOURCE RESISTANCE (Ω) TEMPERATURE (°C) LT1024 • TPC01 LT1024 • TPC02 1024fa 4