Datasheet LT1055, LT1056 (Analog Devices) - 10

LT1055/LT1056
APPLICATIONS INFORMATION
printed circuit board is required. Bulk leakage reduction ing an LT1056 at ±5V supplies or with a 20°C/W case- depends on the guard ring width. to-ambient heat sink reduces 0.1Hz to 10Hz noise from The LT1055/LT1056 has the lowest offset voltage of any typically 2.5µVP-P (±15V, free-air) to 1.5µVP-P. Similiarly, JFET input op amp available today. However, the offset the noise of an LT1055 will be 1.8µVP-P typically because voltage and its drift with time and temperature are still of its lower power dissipation and chip temperature. not as good as on the best bipolar amplifiers because the
High Speed Operation
transconductance of FETs is considerably lower than that of bipolar transistors. Conversely, this lower transcon- Settling time is measured in the test circuit shown. This test ductance is the main cause of the significantly faster speed configuration has two features which eliminate problems performance of FET input op amps. common to settling time measurments: (1) probe capaci- tance is isolated from the “false summing” node, and (2) Offset voltage also changes somewhat with temperature it does not require a “flat top” input pulse since the input cycling. The AM grades show a typical 20µV hysteresis pulse is merely used to steer current through the diode (30µV on the M grades) when cycled over the –55°C to bridges. For more details, please see Application Note 10. 125°C temperature range. Temperature cycling from 0°C to 70°C has a negligible (less than 10µV) hysteresis effect. As with most high speed amplifiers, care should be taken with supply decoupling, lead dress and component placement. The offset voltage and drift performance are also affected by packaging. In the plastic N8 package the molding com- When the feedback around the op amp is resistive (RF), pound is in direct contact with the chip, exerting pressure a pole will be created with RF, the source resistance and on the surface. While NPN input transistors are largely capacitance (RS, CS), and the amplifier input capacitance unaffected by this pressure, JFET device matching and drift (CIN ≈ 4pF). In low closed-loop gain configurations and are degraded. Consequently, for best DC performance, as with RS and RF in the kilohm range, this pole can create shown in the typical performance distribution plots, the excess phase shift and even oscillation. A small capaci- TO-5 H package is recommended. tor (CF) in parallel with RF eliminates this problem. With RS (CS + CIN) = RFCF, the effect of the feedback pole is
Noise Performance
completely removed. The current noise of the LT1055/LT1056 is practically CF immeasurable at 1.8fA/√Hz. At 25°C it is negligible up to 1G of source resistance, RS (compound to the noise of RF RS). Even at 125°C it is negligible to 100M of RS. The voltage noise spectrum is characterized by a low 1/f – corner in the 20Hz to 30Hz range, significantly lower than C R IN OUTPUT S CS on other competitive JFET input op amps. Of particular + interest is the fact that with any JFET IC amplifier, the LT1055/56 AI03 frequency location of the 1/f corner is proportional to
Phase Reversal Protection
the square root of the internal gate leakage currents and, therefore, noise doubles every 20°C. Furthermore, as il- Most industry standard JFET input op amps (e.g., LF155/ lustrated in the noise versus chip temperature curves, the LF156, LF351, LF411, OP15/16) exhibit phase reversal at 0.1Hz to 10Hz peak-to-peak noise is a strong function of the output when the negative common mode limit at the temperature, while wideband noise (f input is exceeded (i.e., from –12V to –15V with ±15V sup- O = 1kHz) is practi- cally unaffected by temperature. plies). This can cause lock-up in servo systems. As shown below, the LT1055/LT1056 does not have this problem Consequently, for optimum low frequency noise, chip due to unique phase reversal protection circuitry (Q1 on temperature should be minimized. For example, operat- simplified schematic). 10556fd 10 For more information www.linear.com/LT1055 Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Applications Information Typical Applications Simplified schematic Package Description Revision History Typical Application Related Parts