Datasheet LTC3126 (Analog Devices) - 10

LTC3126
pin FuncTions (QFN/TSSOP) VCC, PVCC (Pins 2, 3/Pins 5, 6):
Internal Linear Regula- application (i.e., if there is no resistor from VREF to ground) tor Output and Power Supply for the Low Voltage Control then the VREF pin must be connected to VCC. Circuitry in the IC. Internal linear regulators generate a
GND (Pin 8/ Pin 11):
Signal Ground. This pin is the ground regulated voltage on these pins from either VIN1, VIN2 or connection for the control circuitry of the IC and must be EXTVCC. VCC and PVCC must be connected together in the tied to ground. application. A 4.7μF or larger bypass capacitor must be connected between these pins and ground. The VCC rail
FB (Pin 9/Pin 12):
Feedback Voltage Input. A resistor di- remains powered in shutdown and can be used to supply vider connected to this pin establishes the output voltage up to 1mA to external loads. of the buck converter. Care should be taken in the rout- ing of connections to this pin in order to minimize stray
EXTVCC (Pin 4/Pin 7):
VCC Regulator Bootstrapping Pin. If coupling to the SW, BST1, BST2, COM1 and COM2 pins. this pin is forced to 3.15V or greater then EXTVCC will be used to power the internal VCC rail. Typically, the EXTVCC
RT (Pin 10/Pin 13):
Switching Frequency Programming input is connected to the buck converter output voltage. Pin. A resistor placed from this pin to ground sets the Bootstrapping the internal VCC rail in this fashion provides switching frequency of the buck converter. a significant efficiency advantage and reduced quiescent
PGOOD (Pin 11/Pin 14):
Open-Drain Power Good Indicator current especially in applications with high input voltage for the Buck Converter Output Voltage. This output is driven and low output voltage. If the EXTVCC pin is left open then low if the buck converter output voltage is more than 8.7% the VCC rail will be powered from the VIN1 and VIN2 pins. below the regulation voltage or more than 9.8% above
VSET1, VSET2 (Pins 5, 6/Pins 8, 9):
Programming Pins for the regulation voltage. The PGOOD pin is also driven low the UVLO Thresholds on VIN1 and VIN2. The voltage on whenever the buck converter is disabled. The maximum the VSET1 and VSET2 pins programs the UVLO threshold voltage that can be applied to the PGOOD pin is 5.5V. for the power source inputs VIN1 and VIN2, respectively. A
PRIORITY (Pin 12/Pin 15):
Open-Drain Output Indicat- voltage between zero and 1V programs a corresponding ing That the Priority Input (V UVLO threshold between zero and 20V. However, there IN1) Is Being Utilized. The PRIORITY pin is driven low if the part is enabled and the is also a fixed internal UVLO threshold (typically 2.34V) buck converter is operating from the priority input, V on each input which is always in effect. The voltage on IN1. In disable (ENA low) the PRIORITY pull-down is disabled, VSET1,2 can be set using a resistor divider from the accu- allowing the pin to float. The maximum voltage that can rate reference output, VREF. Grounding VSET1,2 will allow be applied to the PRIORITY pin is 5.5V. the respective input VIN1,2 to be used down to the fixed, internal UVLO threshold.
PVIN2 (Pin 13/Pin 16):
Secondary Power Source Input for the Buck Converter. In priority mode (DIODE pin low)
VREF (Pin 7/Pin 10):
Voltage Reference Output for Pow- the buck converter will only operate from this input if the ering Resistor Dividers to Set the VSET1 and VSET2 Inputs. priority input power source is under voltage. This pin must The voltage at this pin is regulated by the IC to maintain a be bypassed with a 4.7µF or larger ceramic capacitor to high precision, temperature stable 1.0V output. Resistive ground. If the PV dividers from the V IN2 input will be subjected to inductive REF pin can be used to set the voltage at shorts to ground, then a power Schottky diode must be the VSET1 and VSET2 pins and thereby program the UVLO added from ground to PV threshold for each input. The V IN2 to prevent this pin from being REF output may also be used driven below ground. as a general purpose voltage reference in the application, providing a temperature stable reference for comparators,
ENA (Pin 14/Pin 17):
Enable Input. Forcing the ENA pin DACs or other functions. The total current drawn from this low disables the input voltage comparators, the VREF pin pin must be limited to 1mA and the total capacitive load driver and the buck converter. The VCC rail remains powered should be limited to 470pF. If this pin is not used in the in disable and therefore ENA can be connected to VCC to 3126f 10 For more information www.linear.com/LTC3126 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Quick Reference Operation Applications Information Typical Applications Package Description Typical Application Related Parts