Datasheet LT8612 (Analog Devices) - 8
| 制造商 | Analog Devices |
| 描述 | 42V, 6A Synchronous Step-Down Regulator with 3μA Quiescent Current |
| 页数 / 页 | 22 / 8 — PIN FUNCTIONS SYNC (Pin 1):. SW (Pins 15, 16, 17, 18, 19):. BST (Pin … |
| 文件格式/大小 | PDF / 365 Kb |
| 文件语言 | 英语 |
PIN FUNCTIONS SYNC (Pin 1):. SW (Pins 15, 16, 17, 18, 19):. BST (Pin 20):. TR/SS (Pin 2):. INTV. CC (Pin 21):. BIAS (Pin 22):
该数据表的模型线
文件文字版本
LT8612
PIN FUNCTIONS SYNC (Pin 1):
External Clock Synchronization Input.
SW (Pins 15, 16, 17, 18, 19):
The SW pins are the Ground this pin for low ripple Burst Mode operation at outputs of the internal power switches. Tie these pins low output loads. Tie to a clock source for synchroniza- together and connect them to the inductor and boost tion to an external frequency. Apply a DC voltage of 3V or capacitor. This node should be kept small on the PCB for higher or tie to INTVCC for pulse-skipping mode. When good performance. in pulse-skipping mode, the IQ will increase to several
BST (Pin 20):
This pin is used to provide a drive volt- hundred µA. Do not float this pin. age, higher than the input voltage, to the topside power
TR/SS (Pin 2):
Output Tracking and Soft-Start Pin. This switch. Place a 0.1µF boost capacitor as close as possible pin allows user control of output voltage ramp rate during to the IC. start-up. A TR/SS voltage below 0.97V forces the LT8612
INTV
to regulate the FB pin to equal the TR/SS pin voltage.
CC (Pin 21):
Internal 3.4V Regulator Bypass Pin. The internal power drivers and control circuits are pow- When TR/SS is above 0.97V, the tracking function is dis- ered from this voltage. INTV abled and the internal reference resumes control of the CC maximum output cur- rent is 20mA. Do not load the INTV error amplifier. An internal 2.1μA pull-up current from CC pin with external circuitry. INTV INTV CC current will be supplied from BIAS if CC on this pin allows a capacitor to program output V voltage slew rate. This pin is pulled to ground with an BIAS > 3.1V (Typical), otherwise current will be drawn from V internal 230Ω MOSFET during shutdown and fault condi- IN. Voltage on INTVCC will vary between 2.8V and 3.4V when V tions; use a series resistor if driving from a low impedance BIAS is between 3.0V and 3.6V. Decouple this pin to power ground with at least a 1μF low ESR ceramic output. This pin may be left floating if the tracking function capacitor placed close to the IC. is not needed.
BIAS (Pin 22):
The internal regulator will draw current
RT (Pin 3):
A resistor is tied between RT and ground to from BIAS instead of V set the switching frequency. IN when BIAS is tied to a voltage higher than 3.1V. For output voltages of 3.3V and above
EN/UV (Pin 4):
The LT8612 is shut down when this pin this pin should be tied to VOUT. If this pin is tied to a sup- is low and active when this pin is high. The hysteretic ply other than VOUT use a 1µF local bypass capacitor on threshold voltage is 1.00V going up and 0.96V going this pin. down. Tie to VIN if the shutdown feature is not used. An
PG (Pin 23):
The PG pin is the open-drain output of an external resistor divider from VIN can be used to program internal comparator. PG remains low until the FB pin is a VIN threshold below which the LT8612 will shut down. within ±9% of the final regulation voltage, and there are
VIN (Pins 5, 6, 7):
The VIN pins supply current to the no fault conditions. PG is valid when VIN is above 3.4V, LT8612 internal circuitry and to the internal topside power regardless of EN/UV pin state. switch. These pins must be tied together and be locally
FB (Pin 24):
The LT8612 regulates the FB pin to 0.970V. bypassed. Be sure to place the positive terminal of the Connect the feedback resistor divider tap to this pin. Also, input capacitor as close as possible to the VIN pins, and connect a phase lead capacitor between FB and V the negative capacitor terminal as close as possible to OUT. Typically, this capacitor is 4.7pF to 10pF. the PGND pins.
NC (Pins 25 to 28):
No Connect. These pins should be
PGND (Pins 8, 9, 10):
Power Switch Ground. These pins connected to PCB Ground. are the return path of the internal bottom-side power switch and must be tied together. Place the negative ter- minal of the input capacitor as close to the PGND pins as possible. 8612fa 8 For more information www.linear.com/LT8612 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Block Diagram Operation Applications Information Typical Applications Package Description Typical Application Related Parts
PIN FUNCTIONS SYNC (Pin 1):
External Clock Synchronization Input.
SW (Pins 15, 16, 17, 18, 19):
The SW pins are the Ground this pin for low ripple Burst Mode operation at outputs of the internal power switches. Tie these pins low output loads. Tie to a clock source for synchroniza- together and connect them to the inductor and boost tion to an external frequency. Apply a DC voltage of 3V or capacitor. This node should be kept small on the PCB for higher or tie to INTVCC for pulse-skipping mode. When good performance. in pulse-skipping mode, the IQ will increase to several
BST (Pin 20):
This pin is used to provide a drive volt- hundred µA. Do not float this pin. age, higher than the input voltage, to the topside power
TR/SS (Pin 2):
Output Tracking and Soft-Start Pin. This switch. Place a 0.1µF boost capacitor as close as possible pin allows user control of output voltage ramp rate during to the IC. start-up. A TR/SS voltage below 0.97V forces the LT8612
INTV
to regulate the FB pin to equal the TR/SS pin voltage.
CC (Pin 21):
Internal 3.4V Regulator Bypass Pin. The internal power drivers and control circuits are pow- When TR/SS is above 0.97V, the tracking function is dis- ered from this voltage. INTV abled and the internal reference resumes control of the CC maximum output cur- rent is 20mA. Do not load the INTV error amplifier. An internal 2.1μA pull-up current from CC pin with external circuitry. INTV INTV CC current will be supplied from BIAS if CC on this pin allows a capacitor to program output V voltage slew rate. This pin is pulled to ground with an BIAS > 3.1V (Typical), otherwise current will be drawn from V internal 230Ω MOSFET during shutdown and fault condi- IN. Voltage on INTVCC will vary between 2.8V and 3.4V when V tions; use a series resistor if driving from a low impedance BIAS is between 3.0V and 3.6V. Decouple this pin to power ground with at least a 1μF low ESR ceramic output. This pin may be left floating if the tracking function capacitor placed close to the IC. is not needed.
BIAS (Pin 22):
The internal regulator will draw current
RT (Pin 3):
A resistor is tied between RT and ground to from BIAS instead of V set the switching frequency. IN when BIAS is tied to a voltage higher than 3.1V. For output voltages of 3.3V and above
EN/UV (Pin 4):
The LT8612 is shut down when this pin this pin should be tied to VOUT. If this pin is tied to a sup- is low and active when this pin is high. The hysteretic ply other than VOUT use a 1µF local bypass capacitor on threshold voltage is 1.00V going up and 0.96V going this pin. down. Tie to VIN if the shutdown feature is not used. An
PG (Pin 23):
The PG pin is the open-drain output of an external resistor divider from VIN can be used to program internal comparator. PG remains low until the FB pin is a VIN threshold below which the LT8612 will shut down. within ±9% of the final regulation voltage, and there are
VIN (Pins 5, 6, 7):
The VIN pins supply current to the no fault conditions. PG is valid when VIN is above 3.4V, LT8612 internal circuitry and to the internal topside power regardless of EN/UV pin state. switch. These pins must be tied together and be locally
FB (Pin 24):
The LT8612 regulates the FB pin to 0.970V. bypassed. Be sure to place the positive terminal of the Connect the feedback resistor divider tap to this pin. Also, input capacitor as close as possible to the VIN pins, and connect a phase lead capacitor between FB and V the negative capacitor terminal as close as possible to OUT. Typically, this capacitor is 4.7pF to 10pF. the PGND pins.
NC (Pins 25 to 28):
No Connect. These pins should be
PGND (Pins 8, 9, 10):
Power Switch Ground. These pins connected to PCB Ground. are the return path of the internal bottom-side power switch and must be tied together. Place the negative ter- minal of the input capacitor as close to the PGND pins as possible. 8612fa 8 For more information www.linear.com/LT8612 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Block Diagram Operation Applications Information Typical Applications Package Description Typical Application Related Parts