Datasheet LTC3639 (Analog Devices) - 6

制造商Analog Devices
描述High Efficiency, 150V 100mA Synchronous Step-Down Regulator
页数 / 页26 / 6 — PIN FUNCTIONS SW (Pin 1):. IN (Pin 3):. ISET (Pin 11):. FBO (Pin 5):. …
文件格式/大小PDF / 294 Kb
文件语言英语

PIN FUNCTIONS SW (Pin 1):. IN (Pin 3):. ISET (Pin 11):. FBO (Pin 5):. VPRG2, VPRG1 (Pins 6, 7):. OVLO (Pin 12):

PIN FUNCTIONS SW (Pin 1): IN (Pin 3): ISET (Pin 11): FBO (Pin 5): VPRG2, VPRG1 (Pins 6, 7): OVLO (Pin 12):

该数据表的模型线

文件文字版本

LTC3639
PIN FUNCTIONS SW (Pin 1):
Switch Node Connection to Inductor. This its nominal value of 5µA. The output voltage ramp time pin connects to the drains of the internal power MOSFET from zero to its regulated value is 1ms for every 6.25nF switches. of capacitance from SS to GND. If left floating, the ramp
V
time defaults to an internal 1ms soft-start.
IN (Pin 3):
Main Supply Pin. A ceramic bypass capacitor should be tied between this pin and GND.
ISET (Pin 11):
Peak Current Set Input. A resistor from this
FBO (Pin 5):
Feedback Comparator Output. The typical pin to ground sets the peak current comparator threshold. pull-up current is 20µA. The typical pull-down impedance Leave floating for the maximum peak current (230mA is 70Ω. typical) or short to ground for minimum peak current (25mA typical). The maximum output current is one-half
VPRG2, VPRG1 (Pins 6, 7):
Output Voltage Selection. Short the peak current. The 5µA current that is sourced out of both pins to ground for a resistive divider programmable this pin when switching is reduced to 1µA in sleep. Op- output voltage. Short VPRG1 to SS and short VPRG2 to tionally, a capacitor can be placed from this pin to GND ground for a 5V output voltage. Short VPRG1 to ground to trade off efficiency for light load output voltage ripple. and short VPRG2 to SS for a 3.3V output voltage. Short See Applications Information. both pins to SS for a 1.8V output voltage.
OVLO (Pin 12):
Overvoltage Lockout Input. Connect to
GND (Pin 8, 16, Exposed Pad Pin 17):
Ground. The ex- the input supply through a resistor divider to set the over- posed pad must be soldered to the PCB ground plane for voltage lockout level. A voltage on this pin above 1.21V rated thermal performance. disables the internal MOSFET switches. Normal operation
V
resumes when the voltage on this pin decreases below
FB (Pin 9):
Output Voltage Feedback. When configured for an adjustable output voltage, connect to an external 1.10V. Exceeding the OVLO lockout threshold triggers a resistive divider to divide the output voltage down for soft-start reset, resulting in a graceful recovery from an comparison to the 0.8V reference. For the fixed output input supply transient. Tie this pin to ground if the over- configuration, directly connect this pin to the output. voltage is not used.
SS (Pin 10):
Soft-Start Control Input. A capacitor to
RUN (Pin 14):
Run Control Input. A voltage on this pin ground at this pin sets the output voltage ramp time. A above 1.21V enables normal operation. Forcing this pin 50µA current initially charges the soft-start capacitor until below 0.7V shuts down the LTC3639, reducing quiescent switching begins, at which time the current is reduced to current to approximately 1.4µA. Optionally, connect to the input supply through a resistor divider to set the under- voltage lockout. 3639fc 6 For more information www.linear.com/LTC3639 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information Typical Applications Package Description Revision History Typical Application Related Parts