Datasheet LT3976 (Analog Devices) - 9

LT3976
pin FuncTions (MSE/UDD) FB (Pin 1/Pins 23, 24):
The LT3976 regulates the FB pin
VIN (Pins 10, 11, 12/Pins 13, 14, 15):
The VIN pin sup- to 1.197V. Connect the feedback resistor divider tap to this plies current to the LT3976’s internal circuitry and to the pin. Also, connect a phase lead capacitor between FB and internal power switch. These pins must be locally bypassed. the output. Typically, this capacitor is 10pF.
EN (Pin 13/Pin 16):
The part is in shutdown when this
SS (Pin 2/Pin 1):
A capacitor is tied between SS and ground pin is low and active when this pin is high. The hysteretic to slowly ramp up the peak current limit of the LT3976 on threshold voltage is 1.08V going up and 1.02V going down. start-up. There is an internal 1.8μA pull-up on this pin. The EN threshold is only accurate when VIN is above 4.3V. The soft-start capacitor is actively discharged when the If VIN is lower than 3.9V, internal UVLO will place the part EN pin goes low, during undervoltage lockout or thermal in shutdown. Tie to VIN if shutdown feature is not used. shutdown. Float this pin to disable soft-start.
RT (Pin 14/Pin 18):
A resistor is tied between RT and
OUT (Pin 3/Pin 2):
This pin is an input to the dropout ground to set the switching frequency. comparator which maintains a minimum dropout of
PG (Pin 15/Pin 19):
The PG pin is the open-drain output of 500mV between VIN and OUT. The OUT pin connects to an internal comparator. PGOOD remains low until the FB the anode of the internal boost diode. This pin also sup- pin is within 8.4% of the final regulation voltage. PGOOD plies the current to the LT3976’s internal regulator when is valid when V OUT is above 3.2V. Connect this pin to the output when IN is above 2V. the programmed output voltage is less than 16V.
SYNC (Pin 16/Pin 20):
This is the external clock synchro- nization input. Ground this pin for low ripple Burst Mode
BOOST (Pin 4/Pin 4):
This pin is used to provide a drive operation at low output loads. Tie to a clock source for voltage, higher than the input voltage, to the internal bipolar synchronization, which will include pulse skipping at low NPN power switch. output loads. When in pulse-skipping mode, quiescent
SW (Pins 5, 6, 7/Pins 6, 7, 8):
The SW pin is the output of current increases to 11µA in a typical application at no an internal power switch. Connect these pins to the induc- load. Do not float this pin. tor, catch diode, and boost capacitor. An R-C snubber to
GND (Exposed Pad Pin 17/Pin 21, Exposed Pad Pin 25):
GND is needed to ensure robustness under all conditions. Ground. The exposed pad must be soldered to the PCB. Typical values are 2Ω and 470pF.
NC (Pins 8, 9/Pins 3, 5, 9-12, 17, 22):
No Connects. These pins are not connected to internal circuitry. 3976f For more information www.linear.com/3976 9 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information Typical Applications Package Description Typical Application Related Parts