Datasheet LT3988 (Analog Devices) - 9

LT3988
applicaTions inForMaTion STEP-DOWN CONSIDERATIONS
approximated by the following equation:
FB Resistor Network
B DC MAX = B+1 The output voltage is programmed with a resistor divider (refer to the Block Diagram) between the output and the where B is the switch pin current divided by the typical FB pin. Choose the resistors according to: boost current from the BOOST pin current vs switch cur- rent in the Typical Performance Characteristics section.  V  R1=R2 OUT – 1 The maximum operating voltage without pulse-skipping  750mV  is determined by the minimum duty cycle DCMIN: The parallel combination of R1 and R2 should be 20k or V less to minimize bias current errors. The maximum error V OUT + VF IN(PS) = – V DC F + VSW due to V MIN FB bias current is ∆VOUT = IFB(MAX) • R1 with DC
Input Voltage Range
MIN = tON(MIN) • f. The LT3988 will regulate the output current at input volt- The minimum operating voltage is determined either by ages greater than V the LT3988’s undervoltage lockout or by its maximum IN(PS). Exceeding VIN(PS) is safe if the output is in regulation, if the external components have duty cycle. The duty cycle is the fraction of time that the adequate ratings to handle the peak conditions and if the internal switch is on and is determined by the input and peak inductor current does not exceed 2.3A. A saturating output voltages: inductor may further reduce performance. For robust V operation under fault conditions at input voltages of 40V DC = OUT + VF or greater, use an inductor value of 47µH or larger and a VIN – VSW + VF clock rate of 1MHz or lower. where VF is the forward voltage drop of the catch diode Both the maximum and minimum input voltages are a (~0.4V) and VSW is the voltage drop of the internal switch function of the switching frequency and output voltages. (~0.3V at maximum load). This leads to a minimum input Therefore the maximum switching frequency must be set voltage of: to a value that accommodates all the input and output V voltage parameters and must meet both of the following V OUT + VF IN(MIN) = – VF + VSW criteria for each channel: DCMAX V 1 The duty cycle is the fraction of time that the internal f OUT + VF MAX1 = • switch is on during a clock cycle. The maximum duty cycle V t IN(PS) – VSW + VF ON(MIN) is generally given by DCMAX = 1 – tOFF(MIN) • f. However, unlike most fixed frequency regulators, the LT3988 will not  V  1 f OUT + VF switch off at the end of each clock cycle if there is sufficient MAX2 = 1–  V  •  IN(MIN) – VSW + VF  tOFF(MIN) voltage across the boost capacitor (C3 in Figure 1) to fully saturate the output switch. Forced switch-off for a minimum The values of tON(MIN) and tOFF(MIN) are functions of ISW and time will only occur at the end of a clock cycle when the temperature (see chart in the Typical Performance Character- boost capacitor needs to be recharged. This operation istics section). Worst-case values for switch currents greater has the same effect as lowering the clock frequency for a than 0.5A are tON(MIN) = 180ns (for TJ > 125°C tON(MIN) = fixed off time, resulting in a higher duty cycle and lower 200ns) and tOFF(MIN) = 240ns. fMAX1 is the frequency at minimum input voltage. The resultant duty cycle depends which the minimum duty cycle is exceeded. The regulator on the charging times of the boost capacitor and can be will skip ON pulses in order to reduce the overall duty cycle 3988f 9 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information Typical Applications Package Description Typical Application Related Parts