Datasheet LT3971A, LT3971A-5 (Analog Devices) - 8
| 制造商 | Analog Devices |
| 描述 | 38V, 1.3A, 2MHz Step-Down Regulator with 2.2μA Quiescent Current |
| 页数 / 页 | 24 / 8 — PIN FUNCTIONS. BD (Pin 1):. SS (Pin 7):. BOOST (Pin 2):. SW (Pin 3):. RT … |
| 文件格式/大小 | PDF / 361 Kb |
| 文件语言 | 英语 |
PIN FUNCTIONS. BD (Pin 1):. SS (Pin 7):. BOOST (Pin 2):. SW (Pin 3):. RT (Pin 8):. VIN (Pin 4):. PG (Pin 9):. EN (Pin 5):. SYNC (Pin 10):
该数据表的模型线
文件文字版本
LT3971A/LT3971A-5
PIN FUNCTIONS BD (Pin 1):
This pin connects to the anode of the boost
SS (Pin 7):
A capacitor is tied between SS and ground to diode. The BD pin is normally connected to the output. slowly ramp up the peak current limit of the LT3971A on start-up. The soft-start capacitor is only actively discharged
BOOST (Pin 2):
This pin is used to provide a drive volt- when EN is low. The SS pin is released when the EN pin age, higher than the input voltage, to the internal bipolar goes high. Float this pin to disable soft-start. For applica- NPN power switch. tions with input voltages above 25V, add a 100k resistor
SW (Pin 3):
The SW pin is the output of an internal power in series with the soft-start capacitor. switch. Connect this pin to the inductor, catch diode, and
RT (Pin 8):
A resistor is tied between RT and ground to boost capacitor. set the switching frequency.
VIN (Pin 4):
The VIN pin supplies current to the LT3971A’s
PG (Pin 9):
The PG pin is the open-drain output of an internal circuitry and to the internal power switch. This internal comparator. PGOOD remains low until the FB pin pin must be locally bypassed. is within 9% of the final regulation voltage. PGOOD is
EN (Pin 5):
The part is in shutdown when this pin is low valid when the LT3971A is enabled and VIN is above 4.3V. and active when this pin is high. The hysteretic threshold
SYNC (Pin 10):
This is the external clock synchronization voltage is 1.005V going up and 0.975V going down. The EN input. Ground this pin for low ripple Burst Mode operation threshold is only accurate when VIN is above 4.3V. If VIN is at low output loads. Tie to a clock source for synchroni- lower than 4.2V, ground EN to place the part in shutdown. zation, which will include pulse-skipping at low output Tie to VIN if shutdown feature is not used. loads. When in pulse-skipping mode, quiescent current
FB (Pin 6, LT3971A Only):
The LT3971A regulates the FB increases to 1.5mA. pin to 1.19V. Connect the feedback resistor divider tap to
GND (Exposed Pad Pin 11):
Ground. The exposed pad this pin. Also, connect a phase lead capacitor between FB must be soldered to PCB. and VOUT. Typically this capacitor is 10pF.
VOUT (Pin 6, LT3971A-5 Only):
The LT3971A-5 regulates the VOUT pin to 5V. This pin connects to the internal 10MΩ feedback divider that programs the fixed output voltage. 3971af 8 Document Outline FEATURES DESCRIPTION APPLICATIONS TYPICAL APPLICATION ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION ORDER INFORMATION ELECTRICAL CHARACTERISTICS TYPICAL PERFORMANCE CHARACTERISTICS PIN FUNCTIONS BLOCK DIAGRAM OPERATION APPLICATIONS INFORMATION TYPICAL APPLICATIONS PACKAGE DESCRIPTION TYPICAL APPLICATION RELATED PARTS
PIN FUNCTIONS BD (Pin 1):
This pin connects to the anode of the boost
SS (Pin 7):
A capacitor is tied between SS and ground to diode. The BD pin is normally connected to the output. slowly ramp up the peak current limit of the LT3971A on start-up. The soft-start capacitor is only actively discharged
BOOST (Pin 2):
This pin is used to provide a drive volt- when EN is low. The SS pin is released when the EN pin age, higher than the input voltage, to the internal bipolar goes high. Float this pin to disable soft-start. For applica- NPN power switch. tions with input voltages above 25V, add a 100k resistor
SW (Pin 3):
The SW pin is the output of an internal power in series with the soft-start capacitor. switch. Connect this pin to the inductor, catch diode, and
RT (Pin 8):
A resistor is tied between RT and ground to boost capacitor. set the switching frequency.
VIN (Pin 4):
The VIN pin supplies current to the LT3971A’s
PG (Pin 9):
The PG pin is the open-drain output of an internal circuitry and to the internal power switch. This internal comparator. PGOOD remains low until the FB pin pin must be locally bypassed. is within 9% of the final regulation voltage. PGOOD is
EN (Pin 5):
The part is in shutdown when this pin is low valid when the LT3971A is enabled and VIN is above 4.3V. and active when this pin is high. The hysteretic threshold
SYNC (Pin 10):
This is the external clock synchronization voltage is 1.005V going up and 0.975V going down. The EN input. Ground this pin for low ripple Burst Mode operation threshold is only accurate when VIN is above 4.3V. If VIN is at low output loads. Tie to a clock source for synchroni- lower than 4.2V, ground EN to place the part in shutdown. zation, which will include pulse-skipping at low output Tie to VIN if shutdown feature is not used. loads. When in pulse-skipping mode, quiescent current
FB (Pin 6, LT3971A Only):
The LT3971A regulates the FB increases to 1.5mA. pin to 1.19V. Connect the feedback resistor divider tap to
GND (Exposed Pad Pin 11):
Ground. The exposed pad this pin. Also, connect a phase lead capacitor between FB must be soldered to PCB. and VOUT. Typically this capacitor is 10pF.
VOUT (Pin 6, LT3971A-5 Only):
The LT3971A-5 regulates the VOUT pin to 5V. This pin connects to the internal 10MΩ feedback divider that programs the fixed output voltage. 3971af 8 Document Outline FEATURES DESCRIPTION APPLICATIONS TYPICAL APPLICATION ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION ORDER INFORMATION ELECTRICAL CHARACTERISTICS TYPICAL PERFORMANCE CHARACTERISTICS PIN FUNCTIONS BLOCK DIAGRAM OPERATION APPLICATIONS INFORMATION TYPICAL APPLICATIONS PACKAGE DESCRIPTION TYPICAL APPLICATION RELATED PARTS