Datasheet LTC3824 (Analog Devices) - 7
| 制造商 | Analog Devices |
| 描述 | High Voltage Step-Down Controller With 40µA Quiescent Current |
| 页数 / 页 | 16 / 7 — pin FuncTions GND (Pin 1, Exposed Pad Pin 11):. VFB (Pin 5):. SYNC/MODE … |
| 文件格式/大小 | PDF / 385 Kb |
| 文件语言 | 英语 |
pin FuncTions GND (Pin 1, Exposed Pad Pin 11):. VFB (Pin 5):. SYNC/MODE (Pin 2):. SS (Pin 6):. SENSE (Pin 7):. VCC (Pin 8):
该数据表的模型线
文件文字版本
LTC3824
pin FuncTions GND (Pin 1, Exposed Pad Pin 11):
Ground. Exposed pad
VFB (Pin 5):
Error Amplifier Inverting Input. A resistor must be soldered to PCB with expanded metal trace for divider to this pin sets the output voltage. When VFB is rated thermal performance. less than 0.5V, the switching frequency will fold back to
SYNC/MODE (Pin 2):
Synchronization Input and Burst 50kHz to reduce the minimum on-cycle. Mode Operation Enable/Disable. If this pin is left open
SS (Pin 6):
Soft-Start Pin. A capacitor on this pin sets or pulled higher than 2V, Burst Mode operation will be the output ramp-up rate. The typical time for SS to enabled at light load and the typical threshold of entering reach the programmed level is (C • 0.8V)/5µA. Connect Burst Mode operation is one third of current limit. If this a 1MΩ to 10MΩ resistor from SS to ground to reset pin is grounded or the synchronization pulse is present the soft-start capacitor if shutdown mode is used. with a frequency greater than 20kHz then Burst Mode
SENSE (Pin 7):
Current Sense Input Pin. A sense re- operation is disabled and the LTC3824 goes into pulse sistor, R skipping at light loads. To synchronize the LTC3824, the S, from VIN to SENSE sets the current limit to 100mV/R duty cycle of the synchronizing pulse can range from 10% S. to 70% and the synchronizing frequency has to be higher
VCC (Pin 8):
Chip Power Supply. Power supply bypass- than the programmed frequency. ing is required.
RSET (Pin 3):
A resistor from RSET to ground sets the
GATE (Pin 9):
Gate Drive for The External P-channel LTC3824 switching frequency. MOSFET. Typical peak drive current is 2.5A and the drive voltage is clamped to 8V when V
V
CC is higher than 9V.
C (Pin 4):
The Output of the voltage error amplifier gm and the control signal of the current mode PWM control
CAP (Pin 10):
A Low ESR Capacitor of at Least 0.1µF is loop. Switching starts at 0.7V, and higher VC corresponds required from this pin to VCC to bypass the internal regula- to higher inductor current. When VC is pulled below 25mV, tor for biasing the gate driver circuitry. the LTC3824 goes into micropower shutdown. 3824fh For more information www.linear.com/LTC3824 7 Document Outline Features Description Applications Typical Application Absolute Maximum Ratings Pin Configuration Electrical Characteristics Typical Performance Characteristics Applications Information Typical Application Related Parts
pin FuncTions GND (Pin 1, Exposed Pad Pin 11):
Ground. Exposed pad
VFB (Pin 5):
Error Amplifier Inverting Input. A resistor must be soldered to PCB with expanded metal trace for divider to this pin sets the output voltage. When VFB is rated thermal performance. less than 0.5V, the switching frequency will fold back to
SYNC/MODE (Pin 2):
Synchronization Input and Burst 50kHz to reduce the minimum on-cycle. Mode Operation Enable/Disable. If this pin is left open
SS (Pin 6):
Soft-Start Pin. A capacitor on this pin sets or pulled higher than 2V, Burst Mode operation will be the output ramp-up rate. The typical time for SS to enabled at light load and the typical threshold of entering reach the programmed level is (C • 0.8V)/5µA. Connect Burst Mode operation is one third of current limit. If this a 1MΩ to 10MΩ resistor from SS to ground to reset pin is grounded or the synchronization pulse is present the soft-start capacitor if shutdown mode is used. with a frequency greater than 20kHz then Burst Mode
SENSE (Pin 7):
Current Sense Input Pin. A sense re- operation is disabled and the LTC3824 goes into pulse sistor, R skipping at light loads. To synchronize the LTC3824, the S, from VIN to SENSE sets the current limit to 100mV/R duty cycle of the synchronizing pulse can range from 10% S. to 70% and the synchronizing frequency has to be higher
VCC (Pin 8):
Chip Power Supply. Power supply bypass- than the programmed frequency. ing is required.
RSET (Pin 3):
A resistor from RSET to ground sets the
GATE (Pin 9):
Gate Drive for The External P-channel LTC3824 switching frequency. MOSFET. Typical peak drive current is 2.5A and the drive voltage is clamped to 8V when V
V
CC is higher than 9V.
C (Pin 4):
The Output of the voltage error amplifier gm and the control signal of the current mode PWM control
CAP (Pin 10):
A Low ESR Capacitor of at Least 0.1µF is loop. Switching starts at 0.7V, and higher VC corresponds required from this pin to VCC to bypass the internal regula- to higher inductor current. When VC is pulled below 25mV, tor for biasing the gate driver circuitry. the LTC3824 goes into micropower shutdown. 3824fh For more information www.linear.com/LTC3824 7 Document Outline Features Description Applications Typical Application Absolute Maximum Ratings Pin Configuration Electrical Characteristics Typical Performance Characteristics Applications Information Typical Application Related Parts