Datasheet LT3435 (Analog Devices) - 6
| 制造商 | Analog Devices |
| 描述 | High Voltage 3A, 500kHz Step-Down Switching Regulator with 100µA Quiescent Current |
| 页数 / 页 | 24 / 6 — TYPICAL PERFOR A CE CHARACTERISTICS. Dropout Operation. Burst Mode … |
| 文件格式/大小 | PDF / 327 Kb |
| 文件语言 | 英语 |
TYPICAL PERFOR A CE CHARACTERISTICS. Dropout Operation. Burst Mode Operation. No Load 2A Step Response. Step Response
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文件文字版本
LT3435
W U TYPICAL PERFOR A CE CHARACTERISTICS Dropout Operation Dropout Operation Burst Mode Operation
4.0 6 VOUT = 3.3V VOUT = 5V BOOST DIODE = DIODES INC DFLS160 BOOST DIODE = DIODES INC DFLS160 3.5 VOUT 5 50mV/DIV AC-COUPLED 3.0 4 2.5 I 2.0 3 SW 500mA/DIV LOAD CURRENT = 2.5A 1.5 LOAD CURRENT = 2.5A 2 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) 1.0 VIN = 12V 10ms/DIV 3435 G21 LOAD CURRENT = 250mA LOAD CURRENT = 250mA 1 VOUT = 3.3V 0.5 0 0 2 2.5 3 3.5 4 4.5 5 5.5 6 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 7 7.5 INPUT VOLTAGE (V) INPUT VOLTAGE (V) 3435 G19 3435 G20
Burst Mode Operation No Load 2A Step Response Step Response
VOUT V V OUT OUT 50mV/DIV 200mV/DIV 200mV/DIV AC-COUPLED AC-COUPLED AC-COUPLED I I OUT OUT 1A/DIV 1A/DIV ISW 500mA/DIV V VIN = 12V 500µs/DIV 3435 G23 V IN = 12V 10µs/DIV 3435 G22 IN = 12V 500µs/DIV 3435 G24 V V OUT = 3.3V OUT = 3.3V VOUT = 3.3V COUT = 100µF COUT = 100µF ILOAD(DC) = 500mA
U U U PI FU CTIO S NC (Pin 1):
No Connection. inductance on this path will create a voltage spike at switch
SW (Pins 2, 5):
The SW pin is the emitter of the on-chip off, adding to the VCE voltage across the internal NPN. power NPN switch. This pin is driven up to the input pin voltage during switch on time. Inductor current drives the
BOOST (Pin 6):
The BOOST pin is used to provide a drive SW pin negative during switch off time. Negative voltage voltage, higher than the input voltage, to the internal is clamped with the external catch diode. Maximum nega- bipolar NPN power switch. Without this added voltage, the tive switch voltage allowed is –0.8V. typical switch voltage loss would be about 1.5V. The additional BOOST voltage allows the switch to saturate
VIN (Pins 3, 4):
This is the collector of the on-chip power and its voltage loss approximates that of a 0.1Ω FET NPN switch. VIN powers the internal control circuitry when structure. a voltage on the BIAS pin is not present. High di/dt edges occur on this pin during switch turn on and off. Keep the
CT (Pin 7):
A capacitor on the CT pin determines the amount path short from the V of delay time between the PGFB pin exceeding its thresh- IN pin through the input bypass capacitor, through the catch diode back to SW. All trace old (VPGFB) and the PG pin set to a high impedance state. 3435fa 6
W U TYPICAL PERFOR A CE CHARACTERISTICS Dropout Operation Dropout Operation Burst Mode Operation
4.0 6 VOUT = 3.3V VOUT = 5V BOOST DIODE = DIODES INC DFLS160 BOOST DIODE = DIODES INC DFLS160 3.5 VOUT 5 50mV/DIV AC-COUPLED 3.0 4 2.5 I 2.0 3 SW 500mA/DIV LOAD CURRENT = 2.5A 1.5 LOAD CURRENT = 2.5A 2 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) 1.0 VIN = 12V 10ms/DIV 3435 G21 LOAD CURRENT = 250mA LOAD CURRENT = 250mA 1 VOUT = 3.3V 0.5 0 0 2 2.5 3 3.5 4 4.5 5 5.5 6 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 7 7.5 INPUT VOLTAGE (V) INPUT VOLTAGE (V) 3435 G19 3435 G20
Burst Mode Operation No Load 2A Step Response Step Response
VOUT V V OUT OUT 50mV/DIV 200mV/DIV 200mV/DIV AC-COUPLED AC-COUPLED AC-COUPLED I I OUT OUT 1A/DIV 1A/DIV ISW 500mA/DIV V VIN = 12V 500µs/DIV 3435 G23 V IN = 12V 10µs/DIV 3435 G22 IN = 12V 500µs/DIV 3435 G24 V V OUT = 3.3V OUT = 3.3V VOUT = 3.3V COUT = 100µF COUT = 100µF ILOAD(DC) = 500mA
U U U PI FU CTIO S NC (Pin 1):
No Connection. inductance on this path will create a voltage spike at switch
SW (Pins 2, 5):
The SW pin is the emitter of the on-chip off, adding to the VCE voltage across the internal NPN. power NPN switch. This pin is driven up to the input pin voltage during switch on time. Inductor current drives the
BOOST (Pin 6):
The BOOST pin is used to provide a drive SW pin negative during switch off time. Negative voltage voltage, higher than the input voltage, to the internal is clamped with the external catch diode. Maximum nega- bipolar NPN power switch. Without this added voltage, the tive switch voltage allowed is –0.8V. typical switch voltage loss would be about 1.5V. The additional BOOST voltage allows the switch to saturate
VIN (Pins 3, 4):
This is the collector of the on-chip power and its voltage loss approximates that of a 0.1Ω FET NPN switch. VIN powers the internal control circuitry when structure. a voltage on the BIAS pin is not present. High di/dt edges occur on this pin during switch turn on and off. Keep the
CT (Pin 7):
A capacitor on the CT pin determines the amount path short from the V of delay time between the PGFB pin exceeding its thresh- IN pin through the input bypass capacitor, through the catch diode back to SW. All trace old (VPGFB) and the PG pin set to a high impedance state. 3435fa 6